tmsr - Search: fpga

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asciilifeform: hey hey ho ho THAT's where the fpga farms went.

asciilifeform: prolly running on fpga.

trinque will not fall back to abacus until tmsr-fpga exists

asciilifeform: (see logz, we had at least half a dozen 'if fpga actually existed' threads.)

asciilifeform: this is why the only tmsr silicon worth making is an fpga.

asciilifeform: and everybody pretty much uses fpga clusters for actual cryptoanalysis anyway. so elaborate 'let's zap the miners' trickery is ~pointless.

asciilifeform: and they are what is needed to replicate the thing on fpga.

asciilifeform: phf: fpga. is the only reasonable definition.

a111: Logged on 2016-04-22 02:23 phf: so the idea is what drop $500k on an pure documented fpga, hope that maker crowd will help you recoup your costs, use fraction to run tmsr infrastructure? :)

phf: so what's the advantage of fpga based architecture as opposed to someone hypothetically investing quite a bit more than 500k into a high density risc, etc.?

phf: so the idea is what drop $500k on an pure documented fpga, hope that maker crowd will help you recoup your costs, use fraction to run tmsr infrastructure? :) ☟︎

asciilifeform: (modern vendors succumb to the temptation to put a great many special-purpose parts in fpga, e.g., multipliers, even whole cpu cores, etc. i am specifically not talking about their rubbish.)

asciilifeform: fpga is also nice because, in principle, it can be optically inspected

asciilifeform: also 'greenarray' i will nitpick is not an fpga

asciilifeform: analogously, the correct thing to make today would be not merely fpga,

asciilifeform: but then the act is only scarcely different from using fpga.

asciilifeform: fpga also plays well with my 'specificity of diddling' theorem.

asciilifeform: (fpga only became a seriously practical thing, really, in 2000s. you will find them from '90s but on MASSIVE boards with dozens of the same unit)

asciilifeform: if i could make one thing, on a traditional si process, it would be an fpga.

asciilifeform: i actually spent the first ~6 mo. after i bought the lisp machine, trying to rig up, with fpga, a mechanism to read the fucking disk ☟︎

asciilifeform: this is why the sane fpga will have to be produced.

asciilifeform: for ALL fpga.

asciilifeform: sbp ^ there ARE NO FPGA

asciilifeform: sbp: where do you intend to get a usable fpga ?

sbp: I suppose there's always the FPGA route

mircea_popescu: adlai: asciilifeform: would you argue that satoshi should've switched PoW each time a new optimized (ie, gpu, fpga, etc) miner was released, at least, before he sepukkud? <<< whatever he'd argue, it is a fact that YES, satoshi should have been a man rather than an herb, and once he knew things blew up should have called forth the dragon. ☟︎

adlai: asciilifeform: would you argue that satoshi should've switched PoW each time a new optimized (ie, gpu, fpga, etc) miner was released, at least, before he sepukkud?

asciilifeform: mircea_popescu: they are related strictly in the sense where we are likely to get 1980s fabbing capability long before 'modern', but also in the sense where we might have to use fpga or even discrete logic elements before this is all through

mircea_popescu: what he was talking about was that in all fpga/asic designs, the branches are the time waster / heat dissipater

mircea_popescu: "=== RISCV === While this architecture is extremely limited in performance, price, and performance per watt compared to x86, ARM, or POWER, it is also one of the only fully open source CPU architectures available outside of an FPGA. and may eventually be competitive with MIPS in terms of raw performance. Currently there are no RISCV SoCs in production, however projects such as lowRISC aim to change that: http://www.lowrisc.

asciilifeform: that is, if i want to run it on an arch that gets auto-genned on my fpga every morning, i oughta be able to.

asciilifeform: in other 'news,' https://vjordan.info/log/fpga/xc6slx9-die-layout-and-bitstream.html

assbot: The QL Forum • View topic - Native 68k vs Coldfire vs FPGA vs recompilation ? ... ( http://bit.ly/22KRK6t )

asciilifeform: mod6: you could fit 500 of them on a cheap fpga. but you will be using an AMERICAN FPGA

mod6: is it crazy to think that said chip you're talking about be re-constructed on a fpga, perhaps many of them on one fpga?

mircea_popescu: and what, your own head is bad chinese fpga and you misplaced teh keys ?

asciilifeform: (inside is also a xilinx fpga and some sram.)

asciilifeform: 'NSA@home is a fast FPGA-based SHA-1 and MD5 bruteforce cracker. It is capable of searching the full 8-character keyspace (from a 64-character set) in about a day in the current configuration for 800 hashes concurrently, using about 240W of power. This performance is equivalent to over 1500 Athlon FX-60 CPUs, which would take about 250kW.'

asciilifeform: (usg recently jailed some schmuck for 'exporting secret' of fpga.)

asciilifeform: i find the TOTAL absence of documented fpga on the planet , to be interesting.

asciilifeform: and the item would, in all likelihood, have to be an fpga. (that can be sold to heathens)

asciilifeform: (the ultimate thermonuclear version of this is to ~randomly generate~ a cpu arch, instantiate on an fpga ~and generate a compiler~, and compile for THAT! and i was very sad as a student to discover that one cristina cifuentes invented this long before i did)

asciilifeform: take an official lcd tv, attach fpga where the panel ribbon cable was.

asciilifeform: http://log.bitcoin-assets.com/?date=18-02-2016#1409548 << laugh, but as a schoolboy i wanted to build exactly this. even wrote lengthy treatise turd concerning it. even bought fpga (and then realized that i have no way to attach it to a board, 0.5mm pitch) ☝︎

asciilifeform: a few hectares of this, and you have (slow...) fpga...

assbot: Build your own FPGA - Nick's Blog ... ( http://bit.ly/1XoJXbt )

asciilifeform: http://blog.notdot.net/2012/10/Build-your-own-FPGA << 'computronium fabric by the metre'

mircea_popescu: BingoBoingo yeh. course, fpga thing even then counted more like amateur hour than anything.

BingoBoingo: mircea_popescu: I believe so. Isn't he the one who did the FPGA thing with BuzzDave and professed to be doing the ASIC thing?

ascii_butugychag: but i would readily pay 10k for a box with ONLY open fpga

BingoBoingo: Desire for FPGA instead gets you $6 PASCAL machine

ascii_butugychag: this being said, if the thing consisted 100% of ~documented~ fpga fabric, i would buy it

assbot: Logged on 06-02-2016 15:31:33; asciilifeform: http://log.bitcoin-assets.com/?date=06-02-2016#1397691 << fpga fabric. as i described maybe 1,001 times.

asciilifeform: http://log.bitcoin-assets.com/?date=06-02-2016#1397691 << fpga fabric. as i described maybe 1,001 times. ☝︎☟︎

asciilifeform: ^ 'open toolchain fpga' will happen some time after pigs fly over a frozen hell.

ascii_butugychag: quite! nobody will be plagiarizing old verilog from fpga docs to bake this one.

asciilifeform even bought first fpga as a schoolboy without understanding that it will have to be mounted somewhere. still have it.

asciilifeform: mircea_popescu: he's after the legendary 'dragonfly' fpga.

asciilifeform: gabriel_laddel: fpga is pretty much never mounted in a socket (the low end xilinx cpld, e.g., 95xx series, do come in plcc - but high pin count makes this a bitch)

gabriel_laddel: asciilifeform: Isn't the whole purpose of an FPGA that I can program it in place?

ascii_shmoocon: the other thing is that alt with novel pov is a giftwrapped offering to the fella with the largest stash of ready fpga fabric. which is...

asciilifeform: incidentally, why was there never (afaik) an attempt at a laser-programmed fpga ?

assbot: Logged on 01-12-2015 11:15:38; punkman: https://groups.google.com/forum/#!topic/comp.arch.fpga/DDwLWc-hyyg

asciilifeform: http://log.bitcoin-assets.com/?date=01-12-2015#1334537 << famous among aficionados. 'neocad' actually reversed the time's xilinx fpga line. 'had to die.' ☝︎

punkman: https://groups.google.com/forum/#!topic/comp.arch.fpga/DDwLWc-hyyg ☟︎

asciilifeform: 'only a terrorist would demand the full docs for the fpga or a full netlist for the arm!'

vulpes_a_hopital: fpga aside, we've done the fpga thread to death

ascii_field: let them magicpacket my fpga.

assbot: gtaylormb/opl3_fpga · GitHub ... ( http://bit.ly/1NDEIS9 )

mats: https://github.com/gtaylormb/opl3_fpga

assbot: Reversed Engineered Yamaha OPL3 FM Synthesizer in an FPGA playing Doom - YouTube ... ( http://bit.ly/1NDEwSS )

ascii_field: and this is often gnarly and expensive to reverse, because it's on fpga, yes, and might need 500 units to destroy

ascii_field: generally, folks who are obsessed with 'someone may steal my magic algo!!111!!!!' ship the whole shebang on fpga with config in sram, backed with watch battery;

BingoBoingo: If I recall SHA-3 draft FPGA outdates Bitcoin mining FPGA

assbot: 4 results for 'hardcopy fpga' : http://s.b-a.link/?q=hardcopy+fpga

asciilifeform: !s hardcopy fpga

nubbins`: am i incorrect in that AM etc early models essentially just baked an FPGA design?

decimation: asciilifeform: I wish he would have made a slightly-more function version of this thing http://www.excamera.com/sphinx/fpga-j1.html

asciilifeform: but if anyone presently alive could fab a muller gate fpga, it is probably moore.

asciilifeform: (not even speaking of fpga variant here)

asciilifeform: http://log.bitcoin-assets.com/?date=28-07-2015#1214498 << picture the sheer amount of cpu (gpu? fpga? asic?!!) cycles that went into creating that ☝︎

asciilifeform: ... except for my biggest fpga board

asciilifeform: partly this is on account of using 'hardcopy fpga'

ascii_field: a 'doxxed' fpga is entirely useless if you can't get it!

gabriel_laddel: *a fpga...

gabriel_laddel: ^ some people reverse engineered an fpga's bitstream format

asciilifeform: mats: i remember that one - pretty neat! http://www.excamera.com/sphinx/fpga-j1.html << original www of it

asciilifeform: trinque: i'd even argue that fpga is a mis-step historically, and you'd want to start with traditional 'gal' (as pictured here, http://design.iconnect007.media/index.php/article/31256/maxed-out-programmable-logic-part-deux/31259/?skin=design )

asciilifeform: these presently exist, you can go to store and buy. called fpga.

decimation: tried to simulate on fpga as best as he could

ascii_field: as if fpga has ~ever~ (at least since '92 or so) been 'exposed' as anything but the blackest of black boxes

pete_dushenski: give alf a decade or two and we'll have fpga's this useable

ascii_field: kakobrekla: 'hard copy fpga' has fixed metal, rather than sram LUTs for routing matrix. so slightly faster (and significantly cheaper to manufacture) than ordinary fpga

ascii_field: (they are fpga with hardcoded metallization layer)

funkenstein_: wow, no wonder the era of fpga mining didn't last long

ascii_field: considering that to me, the ~whole fucking point~ of fpga is to get a computer which ~i and only i~ define

assbot: Logged on 17-06-2015 17:32:11; ascii_field: (xilinx, altera, actel, etc. ~all~ make the bulk of their revenue by charging rent for 'properties' like 'the right to have a network card' in your fpga)

ascii_field: (xilinx, altera, actel, etc. ~all~ make the bulk of their revenue by charging rent for 'properties' like 'the right to have a network card' in your fpga) ☟︎

ascii_field: i will remind readers that reversing fpga is not impossible, and has been done. but takes ~20 years and chip is usually unobtainable after 5-10 (sooner if vendor learns that you're doing this)