tmsr - Search: fpga

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apeloyee: yes, that would fit no fpga one can buy

apeloyee: your fpga impl will necessarily have multipliers for various sizes of int

asciilifeform: understand that in fpga 'secret shift' is NOT a function that can be 'called', but a physical object that gets instantiated, using thousands of cells, every time you use it.

apeloyee: on fpga, can bit-pack.

asciilifeform: and doesn't even stand a chance of fitting in fpga.

asciilifeform: and incidentally i was not joking when said 32kb, it is fully my intention to eventually put whole thing on fpga where there will be certainly not even half MB of working space.

mircea_popescu: yeah but how't that work, i make a line speed fpga based encrypto/decryptor and use it as a router ?

asciilifeform: ( incidentally fast ffalicious rsa on ~fpga~ is trivial. )

asciilifeform: there's no particular reason why a router oughta contain a few 100MB of unixlike, rather than, say, a few kB of fpga config.

asciilifeform: mats: lattice is the last remaining non-usg-owned fpga house. lizard gosplan terrified that it might get sold and specs for the high density fpga, opened

asciilifeform: if we gotta compute on fpga, to do rsa sanely -- then fpga it is. 8192-bit regs.

asciilifeform: also POSaM (linked device design) is a little antiquated, yes '04 but fpga already existed, why require megabux pci i/o card

asciilifeform: re the archs -- lattice ice is analogous to children's toy 'lego' where you get 9,000 identical bricks; xilinx ( and altera, and the 'adult' lattice fpga on fancy dev boards ) are analogous to... i guess the 'erector' toy, where there are a certain number of fungible pieces, but also ~a~ motor, ~a~ heavy iron base, a quantity of gears, etc. ☟︎

phf: this is beyond me at this point. i'm mostly trying to understand various initricasies of cadr fpga-ing, i'll revisit this thread later

a111: Logged on 2017-08-22 12:25 asciilifeform: but lattice per se is EXACTLY like xilinx, same profit model, closed arch, license 'ip cores'. their larger flagship fpga is exactly like xilinx 'spartan', full of proprietary peripherals, and that's the one that tends to get packaged into devboards with nic etc

phf: right, so ice is basically just the fpga with minimum amount of breadboarding, if we want to pipistrello gottta design our own

phf: asciilifeform: i don't really understand fpga peripherals architecture very well, but you think you could eyeball compare what's available in ice to pipistrello. (i'm curious where there's a limitation as far as porting cadr) http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello#Pipistrello_Rev_2.0_Hardware_Description

asciilifeform: ( https://www.olimex.com/Products/FPGA/iCE40/iCE40-IO/ << iron component of subj )

asciilifeform: trinque: can also mean 'standard fpga, because why the everliving fuck would you do anything to an fpga except to make it larger'

asciilifeform: re fpga ( there were various 'i'ma throw something together, with 11 different closed dramcontroller, nic, etc from xilinx lib ) , a german, and i fughet who else, all similar

a111: Logged on 2017-08-31 21:43 phf: gabriel_laddel_p: it was a form of speech, but it didn't go anywhere with you. i'm saying it's not a lisp machine, because i have a lisp machine on an fpga right here, ron garret saw a demo and thinks it's a lisp machine. he's sold, i'm not, so it stands.

phf: gabriel_laddel_p: it was a form of speech, but it didn't go anywhere with you. i'm saying it's not a lisp machine, because i have a lisp machine on an fpga right here, ron garret saw a demo and thinks it's a lisp machine. he's sold, i'm not, so it stands. ☟︎

gabriel_laddel_p: specifically, when I say "meet in the middle", a fixed CLIM will run just fine on new tsmr hardware reverse engineered fpga lispm with a minimum amount of fuss

asciilifeform: i can grasp the psychology ( psychiatry..? ) of the california folx. yes, imaginary star drive or immortality nanobot pill is 'moar exciting' than real-life little board with fpga...

asciilifeform: there aren't many smaller fpga sold than the 9572.

asciilifeform: kanzure: what means 'shit fpga' ?

asciilifeform: kanzure: believe or not, i keep up with the literature. tell me how to boobytrap fpga.

asciilifeform: kanzure: it's an fpga .

asciilifeform: kanzure: i've always wanted to discuss, with clueful folx, what specifically one ought to put in 'doping trojan' to sabotage an fpga

asciilifeform: i don't recall him ever going from micrograph to fpga bitstream format

kanzure: why took so long for the black ice storm whatever clifford wolfyap fpga stuff?

mircea_popescu: shit i wish we thought of this in the early days of "fpga mining".

a111: Logged on 2017-08-22 06:12 mircea_popescu: http://btcbase.org/log/2017-08-21#1701530 << recall the original "fpga" miners, serials shaved items "while supplies lasted" ?

asciilifeform: http://btcbase.org/log/2017-08-22#1701786 << asic miners. the original 'asics' were actual shaved fpga. the next gen -- were 'hardcopy fpga', the cheapest fab available, where you just get to define metallization layer and naught else ☝︎

asciilifeform: but lattice per se is EXACTLY like xilinx, same profit model, closed arch, license 'ip cores'. their larger flagship fpga is exactly like xilinx 'spartan', full of proprietary peripherals, and that's the one that tends to get packaged into devboards with nic etc ☟︎☟︎

mircea_popescu: http://btcbase.org/log/2017-08-21#1701530 << recall the original "fpga" miners, serials shaved items "while supplies lasted" ? ☝︎☟︎

a111: Logged on 2017-08-21 15:06 phf: pff, russian tech. spec is produced by kiril after sit in room with 2 fpga (such luxury, whole two!) and bread for three months

a111: Logged on 2017-08-21 12:12 spyked: asciilifeform, what do you think of minimal baremetal implementation of Lisp (RISC assembly only) on something like a MIPS core? I might be thinking this in too abstract terms, it's definitely not that easy. but I'm trying to find a middle way between working FPGA Lisp machine and Lisp on unix.

a111: Logged on 2017-08-21 12:05 spyked: ok, so to sum up; 1. get ice40 fpga; 2. run fpga lisp machine (cadr?); work from that towards symbolics/ivory, or the other way around starting from symbolics.

asciilifeform: ice40 leaves a great deal to be desired ( it is VERY small, comparatively, and doesn't come in a no-flash version, and who knows for how long it will remain in print ) but is by far the closest thing that currently exists to the sane fpga.

phf: pff, russian tech. spec is produced by kiril after sit in room with 2 fpga (such luxury, whole two!) and bread for three months ☟︎

asciilifeform: in other, slightly related lulz, http://www.vzpp-s.ru/production/catalog.pdf << ru clones of fairly recent altera fpga !!

phf: right, but you can already do that with, say, fpga cadr. it's not necessarily a shiny experience though

asciilifeform: phf: the notion is to build a box with sufficient ram, horse, capacity to drive xterm, so that you can sit down on it and edit the fpga config per se.

spyked: asciilifeform, lol, yeah, that's why I gave MIPS as an example. but actually, MIPS on FPGA + MIPS Lisp machine implementation might be more work than starting from CADR. that is, not even accounting for RAM and peripherals

spyked: asciilifeform, what do you think of minimal baremetal implementation of Lisp (RISC assembly only) on something like a MIPS core? I might be thinking this in too abstract terms, it's definitely not that easy. but I'm trying to find a middle way between working FPGA Lisp machine and Lisp on unix. ☟︎

asciilifeform: you gotta minimize the delay and specify gates MANUALLY for the specific fpga

spyked: ok, so to sum up; 1. get ice40 fpga; 2. run fpga lisp machine (cadr?); work from that towards symbolics/ivory, or the other way around starting from symbolics. ☟︎

a111: Logged on 2017-08-19 23:57 phf: fwiw, if the goal is to put an existing lisp machine onto an fpga, then i don't think macivory is a particularly good target. the goal would be to run Genera, which is severely lacking sources for critical components.

asciilifeform: phf: i haven't tried the fpga one

mircea_popescu: so you want to implement the software in fpga ?

phf: fwiw, if the goal is to put an existing lisp machine onto an fpga, then i don't think macivory is a particularly good target. the goal would be to run Genera, which is severely lacking sources for critical components. ☟︎

spyked: hm. this is neat stuff. I know opencores had some free Lisp FPGA designs. never tried any of them though.

mircea_popescu: in theory it could be fit on a fpga.

asciilifeform: on fpga even 32768-bit rsa is as snappy as you could want

asciilifeform: and incidentally, open fpga trivially yields sdr.

asciilifeform: well theoretically fpga

asciilifeform: 'oh noez if we start doing heavy lifting with open fpga it will be immediately discontinued'

mircea_popescu: i'm not faulting them for it ; but the matter remains. 100kg and 5KW/h for the battery-powered fpga ? aww!

asciilifeform: ( lattice co.'s whole niche is micropower fpga )

asciilifeform: in other noose, asciilifeform built 'icestorm', 'arachne-pnr', with plain gcc 4.9 ( the only concession to idiocy on the test machine was python3 ) . and even MOST of 'yosys' ( the last step in the ice40 open sores fpga toolchain ) built. in fact, whole thing built, but linker barfs

asciilifeform: in other noose, lotta frustrated fpga aficionados live in #bolix.

asciilifeform: http://btcbase.org/log/2017-08-02#1692922 << i let this slip by somehow. afaik this is STILL unsolved in the open lit. ( 'this' being 'fpga glue for ssd replacement of st506 drive' ) ☝︎

asciilifeform: fpga only

asciilifeform: ( other than by baking into fpga. which 1) introduces the 'which fpga, again' problem 2) if you have fpga, big enough for sparc, you can make up a SANE arch to go in it

asciilifeform: correct. but the answers to these depend SEVERELY on the substrate. for instance, if your thing lives in a fpga, not filling it up doesn't make it cycle any faster. so you want to actually use the available gates, if they can be used productively

asciilifeform: at any rate the published opensparc fpga thing actually worx

asciilifeform: it exists in everybody's 1990s game console, stereo, vcr, etc. and now also in that fpga item.

asciilifeform: ( dark ages proprietary pre-jtag debugger, it seems, implemented in on-board fpga )

asciilifeform: mircea_popescu: smaller fpga, i mean

asciilifeform: asciilifeform was silently sweating over room full of fpga in those dayz.

phf: that fpga receiver is also technically an illegal device. i don't know if that's in the same article, but consumer gps is supposed to cut off signal when traveling above certain speeds or certain altitudes (i don't remember the specifics though)

asciilifeform: phf: handcrafted fpga gps? yes, saw

asciilifeform: but to date i have not even succeeded in building clang ! despite trying a number of times, because the lattice fpga thing needs it

asciilifeform: lol it's about 100msec on decent ( fpga ) iron!111

asciilifeform: i dun think i have quite 5k individual fpga in the parts chest, no

asciilifeform: i have fpga with >1MB ~internal~ sram right here.

asciilifeform: re whitening, it might be interesting to apply 'dragonfly fpga' to 'distinguish sha'd bitstream from nonsha'd'

asciilifeform: ( theoretically -- a comp needs only fpga, a few nics, some memory, and a means of hooking up hdd )

asciilifeform: ( layout for high-speed fpga is a royal bitch )

asciilifeform: not unless author of fpga circuit chooses to arrange it pc-style (and why!)

asciilifeform: in other noose, asciilifeform learned that a very recent chinese fpga board : AX516 ( http://esys.ir/images/img_Item/1158/Files/AX516_usermanual.pdf ) includes RTL8211EG , GB nic !! and cheapo.

asciilifeform: doesn't get moar destructured than fpga...

asciilifeform: now if only someone made honest fpga.

asciilifeform: anyway sane arch was developed in '80s and called... fpga

asciilifeform: the one possible exception might be ~massive~ fpga floor layouts

erlehmann: as far as i can remember, we did not talk about fpga. his example was some company creating your board and not you.

asciilifeform: erlehmann: didja ask him what specifically it would mean to 'subvert' an fpga ahead of time (i.e. when you have no idea what will be loaded into it, and into what cells in particular ) ?

a111: Logged on 2014-12-11 01:52 asciilifeform: decimation: notice that all known fpga manufacturers (xilinx, altera, lattice, a few others) have the same business model

a111: Logged on 2015-06-17 13:17 asciilifeform: you can pick up a textbook and write a dram controller for fpga from first principles - and it won't work. because, for starters, only a small number of output cells in the chip can function on both rising and falling edge of clock cycle (what 'ddr' means) and only xilinx's closed turd knows where they are in the routing fabric;

asciilifeform: i'd still like to replace it with a civilized fpga for which you don't need a 20GB closed source shitware toolchain

a111: 791 results for "fpga", http://btcbase.org/log-search?q=fpga

asciilifeform: !#s fpga

asciilifeform: it's why you'll find coax jacks on high-end fpga boards

mod6: <+asciilifeform> ( you can't do it on fpga. ) << needs actual crystal?

asciilifeform: ( you can't do it on fpga. )

asciilifeform: but basic idea -- nothing other than fpga machine conforms to 'auditable without electron microscope' and 'specificity of diddling'.

asciilifeform: how to architect fpga box is separate conversation, and iirc mircea_popescu had a pretty good handle on it.

asciilifeform: ditch the 'insulators'. asciilifeform asks for 1 thing and 1 thing only hardwarewise -- massive open fpga, coupled to dram slots.