log☇︎
600+ entries in 0.475s
BingoBoingo: Kinda suggests the 2+3 option seems like it could be had sooner than a neutral field of gates FPGA
asciilifeform: mircea_popescu: this is actually how existing ic industry worx, a good half of the 'asics' are actually 'hard copy fpga', recall the early miner derps threads.
asciilifeform: there's no 'bitness' in fpga, it's a bag of gates, if you have enuff of them you can made n-bit addder, divider, whatever one likes
mircea_popescu: now, a 4096 bit native fpga, specifically for rsa-ing and rsa-likes-ing, THAT might be very useful, because there the s-o-d item is major win. ☟︎
asciilifeform: i disagree -- fpga is analogous to gutenberg's movable type; classical 'asic per design' to chinese whole-plate.
mircea_popescu: i believe attempting to go "everything's a fpga because fg worked ok on one" is learning the wrong lesson from fg, in the http://btcbase.org/log/2014-06-02#699427 sense. ☝︎
mircea_popescu: but anyway, for my own use, fpga=wrapper around industrial poverty, somewhat like a painting that came with crayons.
asciilifeform: FG is baked on fpga.
mircea_popescu: there's two possible reasons you don't have a definition for a fpga you're happy with : either we're not yet enough advanced for one (to use, to make, whatever), or that it is ouytright an escher object.
asciilifeform: for that matter current FG is baked on fpga, from evil old xilinx.
asciilifeform: and pretty much the ideal 'nonspecificity of diddling' platform, it is quite impossible to meaningfully boobytrap fpga fabric if you don't have foreknowledge of what will go into it and precisely where.
mircea_popescu: asciilifeform define "fpga" for me.
mircea_popescu: i dunno "fpga" is something that may be sane.
asciilifeform: mircea_popescu: i've outlined several items, historically. will summarize for the l0gz, in order of descending ( per asciilifeform's lights ) universality : 1) sane fpga 2) sane minimal cpu 3) 8192-bit arithmetizer ( a la ye olde weitek! but for ints ) 4) 2+3 , if somehow can be fit into 1 die 5) 1chip carrierless radio ( per thread ) 6) sane ethernet controller .
asciilifeform: which is not so bad, quite enuff for a mips ( or even the old bolix , supposing anyone had the layout for it ) but laughably small for e.g. fpga.
asciilifeform: ( if yer baking cpu, or fpga, or other item large enuff to make the game worth the candles )
a111: Logged on 2015-01-22 06:26 asciilifeform: whateverthefuck fpga cpu << http://www.cs.utah.edu/~elb/cadbook/Chapters/Chapter13/mips.v << mips.
a111: Logged on 2018-10-19 01:04 asciilifeform: amberglint: when i went to his house 10y ago, offered to him to make fpga-ized 'ivory' , 'pro bono', if he'd only cough up with what. answr was approx 'can't , unless my master permits, and he wouldn't'
asciilifeform: amberglint: when i went to his house 10y ago, offered to him to make fpga-ized 'ivory' , 'pro bono', if he'd only cough up with what. answr was approx 'can't , unless my master permits, and he wouldn't' ☟︎☟︎
asciilifeform: non-vonneumann machine potentially changes this, but $farm went broke before asciilifeform was able to fill 42U cabinet with fpga..
a111: Logged on 2018-10-15 09:33 ave1: asciilifeform, http://btcbase.org/log/2018-10-14#1862451, I've been reading through the logs and could find no reference of how you did this. Could this be monitored with an FPGA? (there seem to be MAC level FPGA based routers).
ave1: asciilifeform, http://btcbase.org/log/2018-10-14#1862451, I've been reading through the logs and could find no reference of how you did this. Could this be monitored with an FPGA? (there seem to be MAC level FPGA based routers). ☝︎☟︎
asciilifeform: also somewhat unusually, there's a full datashit for the thing ( i.e. could drive with fpga; and there's a chinese hdmi/dvi board for it, ~20bux )
asciilifeform: i expect decryptions will be the principal cpu expense of running a rsatronic box. at least until the fyootoor day of fpga etc
asciilifeform: d00d had fpga & buncha FETs for taking the outputs to the magic voltage, buck converter for generating same, painstakenly hand-placed ribbon connectors, etc
asciilifeform: heh if we had the giant fpga..
asciilifeform: Mocky: in the past i attempted a fpga rsa also. sadly the 'ice40' would need to be about 250x bigger, for it to be bakeable
asciilifeform: btw if mircea_popescu or somebody else here discovers that asic ( ~actual~ asic, not metallization-fpga ) can nao be baked for a coupla coin, asciilifeform will not cry; quite opposite.
mircea_popescu: the fpga-sanded-off was usg's own fraud division "butterfly labls", with the mafia dorks.
asciilifeform: mircea_popescu: iirc 1st 'btc asic' were entirely fraudulent fpga-with-sanded-top
asciilifeform: then again, who am i to laugh, i burned '13 on hand-built fpga miner. made grand total of 0.6 coin.
asciilifeform: imho 'sane fpga' is closest thing to 'philosopher's stone' accessible with current tech.
asciilifeform: usg.fpga is expensive because 'intellectual property' derpitude.
asciilifeform: it's an egregious problem in cramped fpga.
a111: Logged on 2018-05-17 18:54 asciilifeform: mircea_popescu: if we had any fab capacity to speak of, these'd be the priority items : 1) large homogeneous fpga 2) otp roms 3) 1+2
a111: Logged on 2018-09-04 15:27 asciilifeform: trinque: 'competition' box routes 1G/s from 48 jacks, daisy-chains with 10GB/s snakes, compiles ip filter rules into 1mil+ gate fpga fabric. how do i bake a sucks-less without large fpga ? ( we dun have large fpga, tho we do have working tiny ones )
asciilifeform: trinque: 'competition' box routes 1G/s from 48 jacks, daisy-chains with 10GB/s snakes, compiles ip filter rules into 1mil+ gate fpga fabric. how do i bake a sucks-less without large fpga ? ( we dun have large fpga, tho we do have working tiny ones ) ☟︎
mircea_popescu: and without the hotglue gb nics and without the derpy fpga "we dunno how to use things".
asciilifeform: some of the fancier units have fpga for filtrations
a111: Logged on 2018-07-22 17:07 asciilifeform: interestingly, both tx and rx end is considerably simpler, physically, than conventional periodic radio -- you dun need oscillators, tuners, at all. aside from pulse shaper, whole thing fits in fpga.
asciilifeform: ( isa was a joy to interface, dun even need fpga, 3-4 ttl chips and you're cooking )
fromloper: Ya... if I feel the pain, I own an FPGA I might play with.
asciilifeform: interestingly, both tx and rx end is considerably simpler, physically, than conventional periodic radio -- you dun need oscillators, tuners, at all. aside from pulse shaper, whole thing fits in fpga. ☟︎
asciilifeform: the holy grail would be to stuff this into a fpga. however ice40 isn't even remotely bigenuff.
asciilifeform: trinque: battlefield version of the hypothetical device would need a purpose-baked (fpga) sdr. but for experiment, could use e.g. 'hackrf' ( i have it, but hesitate to recommend it to others, it comes with a massive ball of open sores rubbish, really wants an ab initio driver , ars longa, etc )
asciilifeform: if it wasn't clear from the turdolade earlier, i'll note for the record : their published 'loader' is not ~entirely~ unrelated to the live one; it is, i suspect, prototype, from the fpga days
phf: what's the executable substrate? i mean it's an fpga carrying its own architecture, what's it compiled with?
asciilifeform: ( tho ordinary fpga is moar susceptible to classical pills )
asciilifeform: i find it interesting that google's approach to building cr50 ( 'hardcopy fpga' ) is actually ~moar~ diddleable, via this method, than if they had shipped ordinary fpga
asciilifeform: aside from golden toilet satellite gear makers, it seems to be the fpga folks who most concern with 'single event upset' ( term of art for this item ) , as a flipped bit in fpga config , even down on earth, routinely translates into magicsmokerelease
asciilifeform: mircea_popescu: if i could find a fpga that sits down pad-for-pad, it becomes a $10 problem.
a111: Logged on 2018-06-12 16:03 asciilifeform: but if can put a $5 fpga in its place, it's a 15 min job.
asciilifeform: douchebag: ~in~ fpga. but not an off-the-shelf one, but with LUT filling in mask rom.
mircea_popescu: douchebag, cr50 is, by all appearances, an arm cortex fpga
asciilifeform: the only on-chip secret that'd make a diff, is if there is an iron backdoor left in fpga
asciilifeform: but if can put a $5 fpga in its place, it's a 15 min job. ☟︎
asciilifeform: in re cr50 -- if we find which fpga was the basis, it may be possible to craft pad-for-pad replacement for the fritz.
asciilifeform: soo they ~did~ put oddball crypto logic in the fpga, e.g. https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/g/dcrypto/dcrypto_runtime.c#40 drives it
asciilifeform: so this doesn't exactly narrow down what the base fpga was.
asciilifeform: and you stuff it into a fpga with a couplae custom periphs
asciilifeform: http://btcbase.org/log/2018-06-12#1823375 << except, it ain't a proper arm cortex, but a softcore-arm in (metallization)fpga. cuz i suspect somebody read the Logz re specificity-of-diddling ☝︎
asciilifeform: j2 at least has the virtue of being small, and fitting in ice40 fpga.
asciilifeform: other than as fpga softcore -- where ?
asciilifeform: i, for instance, would like to know which fpga was their starting point. and where its factory test pads are.
asciilifeform: |\n: best suspicion thus far is that it is a 'hardcopy fpga' (cheap, relatively, method for getting chip baked, they apply a custom metallization mask to a stock crystal)
asciilifeform: all i've been able to find is that 1) it is an arm cortex-m , prolly licensed 2) started life as fpga ( see google's src, comments repeatedly refer to earlier vers as 'fpga' , then , later, 'g-chip' )
asciilifeform: the fact that h1 started life as fpga, suggests this.
asciilifeform: https://archive.li/ZtbxL << clue re origin of 'h1'. seems like they took a 'metallization mask' fpga, a la early asicminer crapola, and run licensed cortex-m3 core .
asciilifeform: aaaand 1) nobody makes larger homogeneous fpga 2) is likely to ever ; see thread http://btcbase.org/log/2018-01-11#1769061 . ☝︎
asciilifeform: nao, there ~is~ today something that there wasn't 5y ago, which is the properly-reversed fpga :
asciilifeform: mircea_popescu: if we had any fab capacity to speak of, these'd be the priority items : 1) large homogeneous fpga 2) otp roms 3) 1+2 ☟︎
asciilifeform: ( and in more 'luxurious' fpga, some components have variable delay depending on how configed , even )
asciilifeform: mircea_popescu: this is one of those items that really wants the rsa fpga
asciilifeform: the lack of an fpga where i could go straight to demonstrating this experimentally, is a pretty substantial headache for asciilifeform
asciilifeform: unfortunately i do not have any way to make asic. as for fpga, none exist of the necessary size. ( see e.g. http://btcbase.org/log/2018-01-04#1764242 ) ☝︎
asciilifeform: for an every-transistor-documented xilinx 'virtex' fpga clone ? would pay
a111: Logged on 2018-01-11 16:58 a111: Logged on 2017-09-02 20:02 asciilifeform: re the archs -- lattice ice is analogous to children's toy 'lego' where you get 9,000 identical bricks; xilinx ( and altera, and the 'adult' lattice fpga on fancy dev boards ) are analogous to... i guess the 'erector' toy, where there are a certain number of fungible pieces, but also ~a~ motor, ~a~ heavy iron base, a quantity of gears, etc.
asciilifeform: apeloyee: afaik nobody ever sold a 'sea of gates' fpga/cpld with sram bitstream storage.
asciilifeform: and it's the 1 fpga currently sold that's worth copying ( scaled-up, naturally )
asciilifeform: the only cure for this is to fab own fpga.
a111: Logged on 2017-09-02 20:02 asciilifeform: re the archs -- lattice ice is analogous to children's toy 'lego' where you get 9,000 identical bricks; xilinx ( and altera, and the 'adult' lattice fpga on fancy dev boards ) are analogous to... i guess the 'erector' toy, where there are a certain number of fungible pieces, but also ~a~ motor, ~a~ heavy iron base, a quantity of gears, etc. ☟︎
asciilifeform: ( granted fg itself it is not a general-purpose comp. but the fpga substrate -- is. observe that it is not programmed by being given a series of sequentially-executed instructions. )
asciilifeform: http://btcbase.org/log/2017-12-27#1758913 << it's not the wasted 8kbit or whatnot ( though on e.g. fpga, that's real waste that you can take to the bank...) but the ~ugliness~ ☝︎
asciilifeform: really the endgame of this is 'compile to fpga'
asciilifeform: it's a bad thing if you want 'asic-resistant' or even fpga-resistant
asciilifeform: and if you merely long for the days of 8 hour compiles -- will luvv large fpga wurk.
asciilifeform: ftr supposed 'fpga' with built-in periphs are simply proprietary gluetraps.
asciilifeform: i specifically exclude devices like xilinx and altera series with ~built-in~ pcie -- these are not, properly speaking, fpga
asciilifeform: but meanwhile-er, in not-at-all-noose, asciilifeform briefly looked into the question of what-would-it-take to make a pci-e FG . found ( e.g. https://archive.is/dGtBI and elsewhere, for the curious ) that it is quite impossible to do with lattice 'ice' or any other small fpga; the complexity is bookcase-length ( supposing one could even ~get~ the req'd docs, many are not only payware but protected via disinfo-flooding )
asciilifeform: incidentally i know of at least 1 item that i use that still not depython3ated -- the lattice ice fpga thing
asciilifeform: so what if sha2 chinese die, if fpga-chinese immediately take their place.
asciilifeform: moar concretely they go around propagandizing that if you build a fpga board you gotta use it, because 'mips is patented' ( in what country ? even in usa patent is 25y ) or 'risc-v is simplest' ( uh, nope ) and other idiocy. ☟︎
asciilifeform: meanwhile, in world of ancient fpga, http://www.geekdot.com/category/hardware/transputer/avm-b1 .
spyked: yes. hopefully more than that in the long term (item to be manually translated to e.g. fpga implementation)
asciilifeform: if you have the lattice fpga demo pcb and feel like practice.
asciilifeform: it'd be, incidentally, an ok fpga student project
asciilifeform: http://btcbase.org/log/2017-10-19#1726680 << i'd like a republican chair to sit in too!111 switch, however, if you want GB or above -- does require making own silicon if you want it to meaningfully differ from the extant items . fpga won't cut it clockwise. ☝︎
apeloyee: you don't have fpga that large.
asciilifeform: fpga has a bit muxer and none of the loops will be loops, lol
apeloyee: bbut fpga has little memory!!!1