asciilifeform: a readily-available ~true~ fpga would be the greatest political advance in a century of electronic crud.

asciilifeform: thing is, fpga is fundamentally a very cruel lie

asciilifeform: you can pick up a textbook and write a dram controller for fpga from first principles - and it won't work. because, for starters, only a small number of output cells in the chip can function on both rising and falling edge of clock cycle (what 'ddr' means) and only xilinx's closed turd knows where they are in the routing fabric; ☟︎☟︎☟︎

asciilifeform: it is trickier than first appears, because 'i want the s00p3r-s33kr1t floor plan for $fpga' is turing-complete (that is, whether the trade was an honest one is not resolvable by machine)

asciilifeform: which orbits around deep-packet shenanigans and likes fpga

asciilifeform: the not-so-secret here is that intel wants to bake fpga directly on x86 die

asciilifeform: there was an outfit which sold something quite like this (fpga on sdram stick) and even one in the shape of a cpu, which could sit down in ordinary cpu socket on multisocket mb

asciilifeform: (connection via ram slots is not, as it may appear, lunacy, but could be done with fpga, which would pretend to be a slice of sdram to two boxes at the same time, ignoring refresh cycles and managing locking somehow)

asciilifeform: aha, as on early fpga.

asciilifeform: (then you get: 'fpga' which doesn't give a damn about radiation, can be fabricated with 1940s equipment, etc)

asciilifeform mined his first, and for long time, only bitcoin, on an fpga for which he wrote a very elementary miner, as an exercise

asciilifeform: for another, fpga and the genuine article can never be comparable on account of ruinous delays in the latter

asciilifeform: mircea_popescu: possibly the fpga/dragonfly thread relates.

asciilifeform: mention of xilinx is especially on the point because a bit-flip in fpga routing fabric is catastrophic

asciilifeform: it had a xilinx spartan 1st ed. fpga inside. and was built like a tank.

asciilifeform: or my mips-on-fpga that exists nowhere but my living room

asciilifeform: and especially not if they had used actual ab initio fab instead of 'hard copy fpga'

asciilifeform: kakobrekla: recall my fpga story at conf. II ? same idea

asciilifeform: if i'm buying 'fpga', and he doesn't have the exact bitstream, he's more or less shit out of luck

asciilifeform: sucks for exactly the same reasons as ordinary fpga

asciilifeform: called antifuse fpga

asciilifeform: but in practice, it has. i have a $$$$$ fpga board gathering dust because realized that it is impossible to implement ddr2 controller (and drive any available memory of reasonable density) without reversing the entire chip

asciilifeform: mircea_popescu: an fpga that isn't a usg-proprietary piece of shit would go a long way

asciilifeform: it's a little thing with a 'xilinx' fpga (nonvolatile) and 'ftdi' usb2 diddler

asciilifeform: theer is an 'open bench logic sniffer' (more or less naked fpga, ~50 usd)

asciilifeform: interestingly, fpga dev boards often have bayonet connectors for external clocking.

asciilifeform: whateverthefuck fpga cpu << http://www.cs.utah.edu/~elb/cadbook/Chapters/Chapter13/mips.v << mips. ☟︎

asciilifeform: the mere emission of a 'muhahahaha' - or some more specific activity peculiar to reverse-engineering purloined fpga bitstreams ?

asciilifeform: 'PARASTOO IS INFORMING THAT "CPLD AND FPGA BITSTREAMS" RUNNING THE SECURITY MODULES IN BOTH GROUND STATIONS AND MANY OF THE HOVERING ACTUAL SATELLITES THAT ARE LINKED TO SOME TARGETED NOCs ARE FULLY DECRYPTED ..AND WE FOUND -- WHILE DOING SATANIC LAUGHS -- SOME OF THESE UGLY CODES ARE NOT EVEN COMPATIBLE WITH BASIC NIST'S FIPS SECURITY GRADE GIVEN TO THESE PRODUCTS WITH $+APPLAUSE .'

asciilifeform: i still want that fpga that evolves to live in one particular floor tile of your cellar.

asciilifeform: folks doing actual work with fpga make very light use of the general-purpose routing matrix

asciilifeform: this is because the entire fpga concept, as imagined by n00bs to the subject, does not actually work.

asciilifeform: punkman: [fpga thread] would MIPS be easier than x86? or does the problem lie in connecting the thing to outside world (fast RAM, peripherals, etc) << problem is that you can't make so much as a barrel shifter on any extant fpga without using a closed turd from the vendor - actually, two turds: one in the logic library part itself, other - the synthesis toolchain

asciilifeform: fpga is internally very much like the well-known 'eniac'

asciilifeform: thing is, synthesis for proper asic is nothing like fpga synthesis

asciilifeform: anyone who wants one - can go get (it builds for the larger among the common fpga)

asciilifeform: the latter isn't simply a non-reprogrammable fpga; it has the LUTs of fpga, but with 'wiring' baked into the metallization layers, rather than fpga-style switching fabric

asciilifeform: (an undergrad can throw a mips-compatible fpga core together in a day)

asciilifeform: !s hard copy fpga

asciilifeform: also to prevent taking the design to another fpga.

asciilifeform: at the risk of repeating the last 100+ xilinx threads - the closed architecture of -all- fpga vendors is specifically to enable this 'business model'

asciilifeform: incidentally, fpga work shits straight into the faces of folks who think that 'anything can be slow-prototyped'

asciilifeform: decimation: overpowers << skeptical until demonstrated in field (i.e. x86 pc) rather than laboratory (fpga with custom dram controller)

asciilifeform: the way i understand it, a 100% open fpga, produced in a thousand factories of mutually-antagonistic owners, is the one and only way to 'open computer.'

asciilifeform: the closest thing anyone has conceived off to movable type re: chip design is the fpga concept.

asciilifeform: wasn't speaking of fpga specifically

asciilifeform: if you had cheap chip fab, there would not even be much reason to build fpga !

asciilifeform: decimation: notice that all known fpga manufacturers (xilinx, altera, lattice, a few others) have the same business model ☟︎☟︎

asciilifeform: don't wait for the chinese to copy fpga. they have no reason whatsoever to.

asciilifeform: as i may have once explained, the chicoms have not done this and should not be expected to ever do it, because fpga is profoundly useless in a mass consumer product.

asciilifeform: pci is a paragon of transparency compared with any extant fpga

asciilifeform: where is the open fpga?

asciilifeform: (re: miner asics: anyone who gives a damn can find, in #b-a logs, my reasonably well-supported hypothesis that miner asic never actually -happened.- that is, there are devices, and they - approximately - work, but they are not 'asics' in the traditional sense. more 'hardcopy fpga.' - actual term of art) ☟︎

asciilifeform: mircea_popescu: not only dreamed, but simulated using bizarre terrorist contraption of fpga+dram+flash.

asciilifeform: mircea_popescu: cannot, much as i'd love to, use 486, or bk-0011, or handmade pdp-11 in fpga.

asciilifeform: on fpga emulating a 486?

asciilifeform: e.g., xilinx wants you to prototype on their fpga, and then offers massively-discounted asic process which simply consists of their fpga die plus custom metallization layer.

asciilifeform: decimation: asic << and here's where the turdmeisters win. many 'asic' products on the market presently are actually 'hardcopy fpga'

asciilifeform: this - is fpga 'in a page.'