224 entries in 0.612s
mircea_popescu: i don't know how you can audit a
xilinx chip. but if you did, asciilifeform would definitely be interested in hearing.
mircea_popescu: well, we don't trust
xilinx for critical infreastructure for the ~same reason we don'tr trust windows.
mircea_popescu: so you are trusting
xilinx to actually do what it says ? and this with code that you can't audit ?
a111: Logged on 2017-03-28 15:03 mod6: i did wanna get a few
xilinx boards to play with... but first ill see what I can learn with the other stuff I got. i also bought a soldering iron.
mod6: i did wanna get a few
xilinx boards to play with... but first ill see what I can learn with the other stuff I got. i also bought a soldering iron.
☟︎ mircea_popescu: (lasts, not because chickens will become
xilinx fans, but because the last people who know how it works will die, and then their writings will... BE MOVED TO NEW DIRECTORIES. and that's that.)
mircea_popescu:
xilinx.e-technik.uni-rostock.de___139.30.202.12/ << lol!
a111: Logged on 2014-12-11 01:52 asciilifeform: decimation: notice that all known fpga manufacturers (
xilinx, altera, lattice, a few others) have the same business model
a111: Logged on 2015-06-17 13:17 asciilifeform: you can pick up a textbook and write a dram controller for fpga from first principles - and it won't work. because, for starters, only a small number of output cells in the chip can function on both rising and falling edge of clock cycle (what 'ddr' means) and only
xilinx's closed turd knows where they are in the routing fabric;
mod6: im gonna get me one of these
xilinx boards.
mircea_popescu: well it's unclear what the fuck it'll be, but it's pretty evident, at least to me, that the chinese ARE trying to erode the whole
xilinx tower of ip.
pete_dushenski: o hey
xilinx has market cap of $12 bn aka 1/30th of facebook.
ascii_deadfiber: if i could be arsed i'd compile it in my
xilinx toolchain and see what max clock is
sbp: "and only
xilinx's closed turd knows where they are in the routing fabric" — ugh
gabriel_laddel: To any "hackers" reading the logs - rather than going after hackteam, try
xilinx, lattice semiconductor next time?
ascii_field: and you don't have the ones you might like, but solely the ones the chip came with from
xilinx etc
ascii_field: (and only a paid-up, to the tune of 100K+ usd, or well-cracked,
xilinx toolchain, will even talk to the $200-300 ones)
assbot: Logged on 17-06-2015 17:32:11; ascii_field: (
xilinx, altera, actel, etc. ~all~ make the bulk of their revenue by charging rent for 'properties' like 'the right to have a network card' in your fpga)
ascii_field: (
xilinx, altera, actel, etc. ~all~ make the bulk of their revenue by charging rent for 'properties' like 'the right to have a network card' in your fpga)
☟︎ assbot: Logged on 17-06-2015 13:17:59; asciilifeform: you can pick up a textbook and write a dram controller for fpga from first principles - and it won't work. because, for starters, only a small number of output cells in the chip can function on both rising and falling edge of clock cycle (what 'ddr' means) and only
xilinx's closed turd knows where they are in the routing fabric;
ascii_field: (before anyone spits back the old paper re: the fact of c-gates implemented on
xilinx fabric - go and see how many of them you can fit. and how much room left for interconnects.)
ascii_field: gabriel_laddel: to avoid rehashing ancient thread for a fifth time, stuck at the realization that reversing
xilinx is futile.
ascii_field: at one time there was much crowing re: a '
xilinx fpga backdoor'
ascii_field: mats: neato, there was a similar project for
xilinx 'virtex'
ascii_field: trinque: you're talking about reverse-engineering, a la nvidia driver,
xilinx (see old thread, etc.)
mircea_popescu: asciilifeform: at the risk of repeating the last 100+
xilinx threads <<< basically, there was no torvalds for hardware. yet.
mircea_popescu: asciilifeform:
xilinx ships a set of identially-functioning turdlibraries for both languages. << one wonders how they actually achieved this.
BingoBoingo: Sure, but what sphicter sculpts the
Xilinx turd.
decimation: my understanding is tha altera is generally easier to deal with here, because they actually do their own r&d to produce these 'ip cores', whereas
xilinx tends to contract it out - involving third parties in your product
mircea_popescu: <asciilifeform> you'd have to buy '
xilinx' or 'altera' - the company - to go with the chip. and publicly gut it. << it will happen.
assbot: debit-
xilinx bitstream decompiler project has been vanished? or does someone know the URL | Comp.Arch.FPGA | FPGARelated.com
mircea_popescu: <asciilifeform> bounce: search channel logs re: at least three separate discussions of how this came to be << you know, giving terms like "
xilinx" is better than an empty search entreaty. he doesn't know what to search for.
assbot: NSA Approved Defense-Grade Spartan-6Q FPGA in Production for Highest Level Cryptographic Capabilities Strengthens
Xilinx Secure Leadership - Aug 31, 2011