224 entries in 0.464s
a111: Logged on 2019-04-17 22:45 asciilifeform: i suspect that proprietor of 'gowin' et al is not thinking 'how do i vanquish the reich' but instead 'how do i chisel enuff revenue away from
xilinx to build palace in miami for my 4 sons'. and i betcha already built.
a111: Logged on 2019-04-17 19:26 asciilifeform: in principle it would be trivial to bake a standardized, commoditized fpga. the 'gowin' people could have easily done this, an' published the interconnect scheme and the delay map. BUT what no one knows how to do, is to make this a +ev proposition. observe, the chinese had no interest in trying to commoditize , but instead went 'we'll do exactly what
xilinx does but slightly cheaper , out of chinesium'
mircea_popescu: and the mechanism that'll work on intell will then work on
xilinx, and so on.
mircea_popescu: not the same thing ~at all~ however. for one thing, it comes with the
xilinx shitstack. for the other, it's a sack large enough to contain a car. we're talking about the actual car.
a111: Logged on 2018-06-14 18:51 asciilifeform: trinque: in trips down lulzmemorylane, asciilifeform blew a good % of 2011 on halfcocked attempt to get miner going on surplus-usg boards with
xilinx fpgas (in varying conditions of mutilation)
mircea_popescu: now, it has a whole pile of "intel me" bs (did i mention -
xilinx ?) but nevertheless
nonlinear: Oh, I hope an opensource flow for
Xilinx is achieved.
a111: Logged on 2018-01-11 16:58 a111: Logged on 2017-09-02 20:02 asciilifeform: re the archs -- lattice ice is analogous to children's toy 'lego' where you get 9,000 identical bricks;
xilinx ( and altera, and the 'adult' lattice fpga on fancy dev boards ) are analogous to... i guess the 'erector' toy, where there are a certain number of fungible pieces, but also ~a~ motor, ~a~ heavy iron base, a quantity of gears, etc.
apeloyee: it's the 1 product currently sold, that's worth buying. << and the
xilinx item in 'fuckgoats'?
a111: Logged on 2017-09-02 20:02 asciilifeform: re the archs -- lattice ice is analogous to children's toy 'lego' where you get 9,000 identical bricks;
xilinx ( and altera, and the 'adult' lattice fpga on fancy dev boards ) are analogous to... i guess the 'erector' toy, where there are a certain number of fungible pieces, but also ~a~ motor, ~a~ heavy iron base, a quantity of gears, etc.
☟︎ a111: Logged on 2017-09-02 19:58 asciilifeform: large
xilinx chips also have 'hard' periphs inside, e.g. multers, adders, shifters, various
phf: right, that's the first thought when you have your cadr up. "oh wait, i need to go fuck around with
xilinx tooling to make any kind of changes here)
a111: Logged on 2017-08-22 12:25 asciilifeform: but lattice per se is EXACTLY like
xilinx, same profit model, closed arch, license 'ip cores'. their larger flagship fpga is exactly like
xilinx 'spartan', full of proprietary peripherals, and that's the one that tends to get packaged into devboards with nic etc
a111: Logged on 2017-08-22 12:25 asciilifeform: but lattice per se is EXACTLY like
xilinx, same profit model, closed arch, license 'ip cores'. their larger flagship fpga is exactly like
xilinx 'spartan', full of proprietary peripherals, and that's the one that tends to get packaged into devboards with nic etc
a111: Logged on 2017-08-21 21:30 spyked hates
xilinx with passion. if only because of the bloated software
spyked hates
xilinx with passion. if only because of the bloated software
☟︎ spyked: hm. I'ma read about it. I only used
xilinx FPGAs myself
mircea_popescu: you know, originally tmsr embeddable work was done on
xilinx. recently discovered superior alternative,
mircea_popescu: asciilifeform basuically this crash-safe thing looks like a mostly theoretical
xilinx blob
a111: Logged on 2014-12-11 01:52 asciilifeform: decimation: notice that all known fpga manufacturers (
xilinx, altera, lattice, a few others) have the same business model
a111: Logged on 2015-06-17 13:17 asciilifeform: you can pick up a textbook and write a dram controller for fpga from first principles - and it won't work. because, for starters, only a small number of output cells in the chip can function on both rising and falling edge of clock cycle (what 'ddr' means) and only
xilinx's closed turd knows where they are in the routing fabric;
mod6: <+asciilifeform> even build -- himself. << one of the things im gonna be doing here, maybe with some handholding, is flashing
xilinx chip with your fg.v
mod6: the chip i've got is a '
xilinx spartan XC3S500E'
mod6: i did get that
xilinx platform cable usb deal in the mail too.
mod6: i was thinking about taking my
xilinx board and seeing if I can throw your fg-genesis on there.