tmsr - Search: xilinx

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a111: Logged on 2019-04-17 22:45 asciilifeform: i suspect that proprietor of 'gowin' et al is not thinking 'how do i vanquish the reich' but instead 'how do i chisel enuff revenue away from xilinx to build palace in miami for my 4 sons'. and i betcha already built.

asciilifeform: i suspect that proprietor of 'gowin' et al is not thinking 'how do i vanquish the reich' but instead 'how do i chisel enuff revenue away from xilinx to build palace in miami for my 4 sons'. and i betcha already built. ☟︎

a111: Logged on 2019-04-17 19:26 asciilifeform: in principle it would be trivial to bake a standardized, commoditized fpga. the 'gowin' people could have easily done this, an' published the interconnect scheme and the delay map. BUT what no one knows how to do, is to make this a +ev proposition. observe, the chinese had no interest in trying to commoditize , but instead went 'we'll do exactly what xilinx does but slightly cheaper , out of chinesium'

asciilifeform: in principle it would be trivial to bake a standardized, commoditized fpga. the 'gowin' people could have easily done this, an' published the interconnect scheme and the delay map. BUT what no one knows how to do, is to make this a +ev proposition. observe, the chinese had no interest in trying to commoditize , but instead went 'we'll do exactly what xilinx does but slightly cheaper , out of chinesium' ☟︎

asciilifeform: but if you want deterministic paths, currently yer stuck using the vendor shitware. ( what's worse, even on ye olde xilinx apparently it is impossible to write e.g. a working 200MHz+ dram controller from 1st principles, yer forced to use the vendor's shitware that actually knows the gate delays, to equalize the paths )

asciilifeform: xilinx incidentally has already confessed to resorting to 'cubism'/layered dies, to meet their claimed cell counts.

asciilifeform: not wholly unrelatedly, asciilifeform's semi-automated archaeology birthed a logworthy output recently. seems like in '80s there was an outfit, 'algotronix', that xilinx bought an' killed , to bury the product in patent liquishit. had entirely homogeneous fpga , made from identical ~200-transistor cells ( with simple north-south-east-west tile interconnects, and 1 flipflop inside, configged via 16bit shift register per cell, connecte

asciilifeform: compare with the fg xilinx die , the latter has no fancy package, and is entirely homogeneous at 35kV.

mircea_popescu: and the mechanism that'll work on intell will then work on xilinx, and so on.

asciilifeform: https://archive.is/dn4wT << yet-another xilinx.

asciilifeform: https://archive.is/2OYCk , https://archive.is/nYVUy << ditto, but in re xilinx

asciilifeform: if i wanted to continue using closed shitware, i'd be entirely happily fitting rsatron into my 400,000-LUT xilinx etc

asciilifeform: ( e.g. classic FG , is only 'upgradeable' because xilinx doesn't offer an otp chip )

mircea_popescu: not the same thing ~at all~ however. for one thing, it comes with the xilinx shitstack. for the other, it's a sack large enough to contain a car. we're talking about the actual car.

asciilifeform: ( naturally it's the big-fpga monopolist, xilinx . but it's there. )

asciilifeform: i've built, fwiw, for mips ( 32 an' 64 -wide ), for arm (ditto), even for 'microblaze' ( spoiler: not an actual iron, but xilinx's oddball 'demo cpu', exists nowhere else but 'virtex' demo boards, of which i have an embarrassingly tall pile ) -- but i ain't ever built for s390, or 68k ...

asciilifeform: not even the $1k xilinx'en.

asciilifeform: the other is political, all of the existing vendors obfuscate and keep seekrit the necessary docs to actually program the thing. ice40 happens to have been reversed, but it is ruinously small ( still ~150x bigger than the miniature xilinx i baked FG from, however , but too small even for 4096bit adder )

asciilifeform: for that matter current FG is baked on fpga, from evil old xilinx.

asciilifeform: doubtful, all of the examples i've been able to peek into, are full of xilinx.

a111: Logged on 2018-06-14 18:51 asciilifeform: trinque: in trips down lulzmemorylane, asciilifeform blew a good % of 2011 on halfcocked attempt to get miner going on surplus-usg boards with xilinx fpgas (in varying conditions of mutilation)

asciilifeform: mircea_popescu: iirc we had a thread re this ; the gnarl is roughly similar to xilinx reversing ( they switch chip revisions erry quarter or so, by the time a card is ~acceptably reversed , it is long out of print )

asciilifeform: i'd also like to be rid of xilinx sooner rather than later.

asciilifeform: ice40, unlike the xilinx cplds, also includes 32kB of onboard sram. so possibly can have small cache, or extra registers, or some other useful item.

asciilifeform: it eats 71 of the 72 logic cells in the old xilinx cpld.

asciilifeform: trinque: in trips down lulzmemorylane, asciilifeform blew a good % of 2011 on halfcocked attempt to get miner going on surplus-usg boards with xilinx fpgas (in varying conditions of mutilation) ☟︎

asciilifeform: this one is something like a xilinx but with metal rom instead of the usual LUT rom.

asciilifeform: xilinx datashit says it's an arm7

mircea_popescu: now, it has a whole pile of "intel me" bs (did i mention - xilinx ?) but nevertheless

mircea_popescu: zynq-7000, a xilinx wrapper

nonlinear: Oh, I hope an opensource flow for Xilinx is achieved.

a111: Logged on 2018-01-11 16:49 apeloyee: http://btcbase.org/log/2018-01-04#1764242 << do I understand correctly that there's nowhere to store the result, as there seems to be enough hw adders in an 'ice'?also, it seems that the same authors are trying to reverse some xilinx nao: https://symbiflow.github.io/

asciilifeform: mircea_popescu: re the xilinx reversing attempt , http://btcbase.org/log/2018-01-11#1769036 << prev thread ☝︎

asciilifeform: for an every-transistor-documented xilinx 'virtex' fpga clone ? would pay

a111: Logged on 2018-01-11 16:58 a111: Logged on 2017-09-02 20:02 asciilifeform: re the archs -- lattice ice is analogous to children's toy 'lego' where you get 9,000 identical bricks; xilinx ( and altera, and the 'adult' lattice fpga on fancy dev boards ) are analogous to... i guess the 'erector' toy, where there are a certain number of fungible pieces, but also ~a~ motor, ~a~ heavy iron base, a quantity of gears, etc.

asciilifeform: i still dislike having to use toolchain from hitler to compile the bitstream. and thereby the current fg is the last time i use a xilinx in a product.

apeloyee: it's the 1 product currently sold, that's worth buying. << and the xilinx item in 'fuckgoats'?

asciilifeform: apeloyee: they could in principle try intel-style fascism with built-in rsa sig verifier or the like. but afaik the only vendor to date to attempt any such thing, was xilinx, and it wasn't even in earnest

asciilifeform: the smaller ones are 'sea of gates' as they are intended to be used for glue logic, and emphasize predictable path timing ( the analogous xilinx series is the 95xx , as used in FUCKGOATS )

asciilifeform: apeloyee: the larger chips by lattice co are already xilinx-like

a111: Logged on 2017-09-02 20:02 asciilifeform: re the archs -- lattice ice is analogous to children's toy 'lego' where you get 9,000 identical bricks; xilinx ( and altera, and the 'adult' lattice fpga on fancy dev boards ) are analogous to... i guess the 'erector' toy, where there are a certain number of fungible pieces, but also ~a~ motor, ~a~ heavy iron base, a quantity of gears, etc. ☟︎

a111: Logged on 2017-09-02 19:58 asciilifeform: large xilinx chips also have 'hard' periphs inside, e.g. multers, adders, shifters, various

asciilifeform: http://btcbase.org/log/2018-01-11#1769036 << this is correct, it simply doesn't have enough LUTs to store even the 2 operands, not even speaking of result. however xilinx is a dead end : because it is 1) nonhomogeneous 2) they switch the internals regularly, specifically to prevent a reversing from being useful in the long term. see old xilinx threads in the logs for detail ☝︎

apeloyee: http://btcbase.org/log/2018-01-04#1764242 << do I understand correctly that there's nowhere to store the result, as there seems to be enough hw adders in an 'ice'?also, it seems that the same authors are trying to reverse some xilinx nao: https://symbiflow.github.io/ ☝︎☟︎☟︎

jhvh1: asciilifeform: Xilinx DS065 XC9572 In-system Programmable CPLD Data Sheet: <https://www.xilinx.com/support/documentation/data_sheets/ds065.pdf>; XC9572 -15PQG100C Xilinx Inc. | Integrated Circuits (ICs) | DigiKey: <https://www.digikey.com/product-detail/en/xilinx-inc/XC9572-15PQG100C/122-1445-ND/966626>; XC9572 -15PC44I Xilinx Inc. | Integrated Circuits (ICs) | DigiKey: (1 more message)

asciilifeform: ( you wouldn't call an 'implementation' of e.g. ppc cpu that simply uses xilinx 'virtex' series' built-in ppc core, an implementation. apply same rule to pci.)

asciilifeform: i specifically exclude devices like xilinx and altera series with ~built-in~ pcie -- these are not, properly speaking, fpga

asciilifeform: ( after which xilinx & altera market will look like cisco's -- tame idjits only )

asciilifeform: i had a xilinx board (shaped like pc mobo, with pci even ) that had this feature

phf: right, that's the first thought when you have your cadr up. "oh wait, i need to go fuck around with xilinx tooling to make any kind of changes here)

asciilifeform: re the archs -- lattice ice is analogous to children's toy 'lego' where you get 9,000 identical bricks; xilinx ( and altera, and the 'adult' lattice fpga on fancy dev boards ) are analogous to... i guess the 'erector' toy, where there are a certain number of fungible pieces, but also ~a~ motor, ~a~ heavy iron base, a quantity of gears, etc. ☟︎

asciilifeform: ( and are the reason why xilinx has not been satisfactorily reversed a la ice, and not likely to be before going out of print )

asciilifeform: large xilinx chips also have 'hard' periphs inside, e.g. multers, adders, shifters, various ☟︎

asciilifeform: ( this is a rough measure, because not all LUTs are created equal, naturally, xilinx has somewhat different ones in the cpld series vs 'spartans', and lattice has yet different, and altera -- yet different, etc )

asciilifeform: ( xilinx toolchain shits out this figure in the report )

asciilifeform: phf: if you're content to test parker's cadr, your existing xilinx board oughta do the job

a111: Logged on 2017-08-22 12:25 asciilifeform: but lattice per se is EXACTLY like xilinx, same profit model, closed arch, license 'ip cores'. their larger flagship fpga is exactly like xilinx 'spartan', full of proprietary peripherals, and that's the one that tends to get packaged into devboards with nic etc

asciilifeform: folx who are willing to use lattice's closed shitdevchain buy the larger parts, where the dev boards are comparable to xilinx.

asciilifeform: but smaller than all but the smallest xilinx 'spartan' parts.

asciilifeform: the problem is that it's xilinx.

asciilifeform: you can get ANYTHING you want on a xilinx board, phf

asciilifeform: phf: that looks like a xilinx

asciilifeform: ( rather like xilinx, if you're a reformed xilinxist )

asciilifeform: re fpga ( there were various 'i'ma throw something together, with 11 different closed dramcontroller, nic, etc from xilinx lib ) , a german, and i fughet who else, all similar

asciilifeform: mircea_popescu: if you'd like to pen a 'can haz the pill against your $B 'intellektual property' racket for phreee? ' letter to lattice, go ahead. i did xilinx.

asciilifeform: but lattice per se is EXACTLY like xilinx, same profit model, closed arch, license 'ip cores'. their larger flagship fpga is exactly like xilinx 'spartan', full of proprietary peripherals, and that's the one that tends to get packaged into devboards with nic etc ☟︎☟︎

a111: Logged on 2017-08-21 21:30 spyked hates xilinx with passion. if only because of the bloated software

asciilifeform: i will be phasing xilinx out of my product line entirely, also.

asciilifeform: i last leeched the xilinx hog in 2011 and don't intend to ever update.

spyked hates xilinx with passion. if only because of the bloated software ☟︎

asciilifeform: if you're used to working with, e.g., xilinx 'spartan' or 'virtex' series, it will feel VERY tight.

spyked: hm. I'ma read about it. I only used xilinx FPGAs myself

mircea_popescu: you know, originally tmsr embeddable work was done on xilinx. recently discovered superior alternative,

asciilifeform: it's their ver of the xilinx virtex, full of proprietary special blox of various sorts

asciilifeform: ( these are ubiquitous for xilinx & altera )

asciilifeform: ( not a high bar, but probably enough to say now that next FUCKGOATS will NOT feature a xilinx no moar )

asciilifeform: ( not even substantially slower than xilinx chain. though i have currently nfi re output quality in re path delays )

asciilifeform: ( that doesn't rely on closed xilinx 20GB turdchain to fill, doesn't contain a flash rom, doesn't double as a frying pan )

asciilifeform: the interesting bit is that linked d00dz stuffed it in 60% of cheap xilinx (lx9, i have a pile of'em)

asciilifeform: xilinx + sdram + usb20tron inside.

asciilifeform: summary of noose piece is 'xilinx+GBnic is nao cheap, who wants -- can get'

asciilifeform: dun get quite so hot an' bothered, it's still made of traditional xilinx (which needs the massive toolchain) and still contains sdram ( for which no controller other than xilinx's , works ) but this board is actually useful -- in comparison with my existing aging 'ml501' ( as pictured in http://www.loper-os.org/?p=702 , http://www.loper-os.org/?p=797 )

asciilifeform: to prototype xilinx+GB

asciilifeform: they didn't break anything, it's still a stock xilinx chip

mircea_popescu: asciilifeform basuically this crash-safe thing looks like a mostly theoretical xilinx blob

a111: Logged on 2016-10-03 13:35 asciilifeform: mepian: http://btcbase.org/log/2016-10-03#1551507 << please read the xilinx threads .

a111: Logged on 2014-12-11 01:52 asciilifeform: decimation: notice that all known fpga manufacturers (xilinx, altera, lattice, a few others) have the same business model

a111: Logged on 2015-06-17 13:17 asciilifeform: you can pick up a textbook and write a dram controller for fpga from first principles - and it won't work. because, for starters, only a small number of output cells in the chip can function on both rising and falling edge of clock cycle (what 'ddr' means) and only xilinx's closed turd knows where they are in the routing fabric;

asciilifeform: erlehmann: i manufacture and sell a product ( http://nosuchlabs.com/hardware.html ) with a xilinx cpld in it

a111: 131 results for "xilinx", http://btcbase.org/log-search?q=xilinx

asciilifeform: !#s xilinx

mircea_popescu: xilinx could work as cpu in theory!

asciilifeform: mircea_popescu: next rev of board will have, for lulzies, a not-xilinx

mircea_popescu: asciilifeform xilinx!

mod6: <+asciilifeform> even build -- himself. << one of the things im gonna be doing here, maybe with some handholding, is flashing xilinx chip with your fg.v

mod6: the chip i've got is a 'xilinx spartan XC3S500E'

mod6: i did get that xilinx platform cable usb deal in the mail too.

mod6: i was thinking about taking my xilinx board and seeing if I can throw your fg-genesis on there.