tmsr - Search: fpga

asciilifeform: lobbes: i mined (yes) 1st, on the pile of junkyard fpga i happened to have surrounded self with at the time .

asciilifeform: the arch illustrated by the sim is simple enuff that one could fit it in, e.g., even very modest fpga. which means that nao we have reproducible kernel, gcc, toolchain, etc. for machine that can be baked , if needed, on demand, in whatever qty.

asciilifeform: it'll need, i expect, fpga + usb3 chip (cuz 200MB/sec to properly sample all the pins)

asciilifeform: mp_en_viaje: very similar, how else. asciilifeform's observation was that even 'nvidia, but 50x slower cuz on fpga matrix, still suffices for reasonable gaming' , more like.

asciilifeform: it's a quite large box of fpga, programmed in much same way as asciilifeform prototyped fg.

asciilifeform: most of what's baked at e.g. tmsc, is 'verilog synthed' i.e. essentially same as fpga but w/ masked config bits.

asciilifeform: really one only needs 2 types of ic in the box , fpga and voltage regulators...

asciilifeform: http://btcbase.org/log/2019-04-24#1909719 << was thinking, as result of last wk's thrd, 'sane fpga could just as readily replace heathen gpu as cpu' ☝︎

asciilifeform: http://btcbase.org/log/2019-04-23#1909541 << the published sores aint especially interesting, aside from archaeological pov ( if you have fpga -- yer product is only as clean as that fpga, and there aint any clean ones gettable ; and if there were, why wouldja want to simulate a pdp11 in it ?? ) ☝︎

asciilifeform: tho i do find it interesting, that it is difficult ( unlike on von neumann cpu ) to write a fpga filling that 'worx sometimes'

a111: Logged on 2019-04-17 19:26 asciilifeform: in principle it would be trivial to bake a standardized, commoditized fpga. the 'gowin' people could have easily done this, an' published the interconnect scheme and the delay map. BUT what no one knows how to do, is to make this a +ev proposition. observe, the chinese had no interest in trying to commoditize , but instead went 'we'll do exactly what xilinx does but slightly cheaper , out of chinesium'

asciilifeform did , repeatedly, write, and many yrs ago nao, that the 'reverse fpga' people are solving the wrong problem -- by the time they achieve anyffin, vendor simply replaces the design and laffs

asciilifeform: ( my current understanding, is that it would be actually ~cheaper~ to bake own homogeneous-fpga thing ... )

a111: Logged on 2019-04-17 18:29 asciilifeform: meanwhile, apparently (last yr) in heathendom, https://archive.is/UVbUE << c. wolf , author of the ice40 open fpga toolchain , apparently barfed and 'went naggum'

asciilifeform: 2y ago asciilifeform found a ru firm that cloned altera's larger fpga. they do SAME THING

asciilifeform: the entire biz model of fpga market as it existed since 1990 or so, is based specifically on pulling this kinda scam.

asciilifeform: in principle it would be trivial to bake a standardized, commoditized fpga. the 'gowin' people could have easily done this, an' published the interconnect scheme and the delay map. BUT what no one knows how to do, is to make this a +ev proposition. observe, the chinese had no interest in trying to commoditize , but instead went 'we'll do exactly what xilinx does but slightly cheaper , out of chinesium' ☟︎

asciilifeform: this is why fpga design ~never runs at anywhere near the max switching rate specced by the device vendor. a good synth tool 1) tries to minimize the delays 2) gives you an accurate figure for max clock, and for propagations of individual paths ( if you have e.g. dram hanging off the thing, these are critical )

bvt: the larger fpga - seems to be it https://symbiflow.github.io/prjtrellis-db/ ? last time i checked it was work in progress

asciilifeform: he had plan to dig into the larger fpga from same vendor, and to improve the synth engine, but apparently went nowhere.

a111: Logged on 2015-03-24 18:38 ascii_field: mats: the way the story normally ends is that the reversed fpga becomes quasi-usable nearly the same time it goes out of print and replaced with incompatible version...

asciilifeform: meanwhile, apparently (last yr) in heathendom, https://archive.is/UVbUE << c. wolf , author of the ice40 open fpga toolchain , apparently barfed and 'went naggum' ☝︎☟︎

a111: Logged on 2019-04-12 15:51 asciilifeform: to briefly revisit ~earthling~ gedanken-fpga tho : it is by no means obv. that the arity has to be 4. anyffin you can tile the 2d plane with, is a legit arity. ( and if you permit 2 or moar types of tile -- then even moar possible options. )

a111: Logged on 2019-04-12 14:46 asciilifeform: http://btcbase.org/log/2019-04-12#1908318 << dun confuse the gedanken-fpga lut thrd with the 'ideal alu bus' one. i.e. a 64-bit bus is a set of 64 wires ; a 64-bit ~lut~ otoh is 2^64 sram cells , a planet-sized object , and with 1 lonely flipflop , lol, somewhere inside its molten core

asciilifeform: i'm not even raging on acct of 'draw gedanken-fpga', it can happily live for another year without being drawn. but i had to spend fucking MONTH hand-sweating out http://www.loper-os.org/?p=2875 , and similar

asciilifeform: to briefly revisit ~earthling~ gedanken-fpga tho : it is by no means obv. that the arity has to be 4. anyffin you can tile the 2d plane with, is a legit arity. ( and if you permit 2 or moar types of tile -- then even moar possible options. ) ☟︎

asciilifeform: ^ astro puzzle : calculate the minimal propagation delay in this 'fpga'. ( just how close can one park a jupiter to another before they merge.. etc )

asciilifeform: http://btcbase.org/log/2019-04-12#1908318 << dun confuse the gedanken-fpga lut thrd with the 'ideal alu bus' one. i.e. a 64-bit bus is a set of 64 wires ; a 64-bit ~lut~ otoh is 2^64 sram cells , a planet-sized object , and with 1 lonely flipflop , lol, somewhere inside its molten core ☝︎☟︎

asciilifeform: ( picture, 1st fella to solve the exercises, gets prize, a sample fpga, lol )

asciilifeform: erry type of homogeneous fpga worx on same principle. you have cell, in the cell, a shift register. for simplest example take 17 bits. (will be clear why shortly)

asciilifeform: unlike the idjit heterogeneous fpga sold today, this item'd be a snap to simulate.

asciilifeform: ( before you laff -- sovok in fact did bake fpga. i have a sample. but it was mid-80s state of art, i.e. metallization-programmed )

asciilifeform: not wholly unrelatedly, asciilifeform's semi-automated archaeology birthed a logworthy output recently. seems like in '80s there was an outfit, 'algotronix', that xilinx bought an' killed , to bury the product in patent liquishit. had entirely homogeneous fpga , made from identical ~200-transistor cells ( with simple north-south-east-west tile interconnects, and 1 flipflop inside, configged via 16bit shift register per cell, connecte

asciilifeform: fughetting for a moment fpga : consider ordinary transistor, or even diode. it is not physically possible to bake a 'secretly smart' transistor that does s/mp-pubkey/gavin-pubkey in hopes of being put in somebody's serial port 1 day, and for it to have same analogue characteristics as genuine diode (not even speaking of what it'd look like under microscope)

mp_en_viaje: now imagine a fpga, surrounded by 725 islands, leveraging each one thing, this is net-a that is tcp-ip-b, that'

mp_en_viaje: so : suppose a) tcp/ip is intrinsically, by its very [deliberate, and previously uknown-ly so] design vulnerable to "blowhammer", which is a class of yet undescribed attacks ; suppose your fpga includes an electrically-isolated leverage for a.

asciilifeform: mp_en_viaje: it is entirely possible to sabotage fpga in the e.g. 'philips light bulb' sense, where it burns out after 5000 hrs. or shorts + to - erry month. or similar. these are 'physical' sabotages, and imho uninteresting because indistinguishable from simply shoddy part. the interesting hypothetical mine is a ~logical~ mine.

asciilifeform: asciilifeform's fg test process for freshly-received boards, for instance, included an (unpublished, and won't be published any time soon) set of test circuits for the fpga , that characterized the propagation delays.

a111: Logged on 2019-04-06 23:35 OriansJ: Let us just assume the FPGA was not compromised and leverage it for the bootstrap work at this stage (I'll be going to pure LibreSilicon before I am finished but hey to each their own)

a111: Logged on 2019-04-06 23:26 asciilifeform: the puzzler concerns 'general purpose' sabotaged fpga, rather than case where you know what the victim intends to connect and what protocols etc

a111: Logged on 2019-04-05 23:25 OriansJ: well, I guess a really important question to ask is at what level of lithography people here actually have trust? (1 transistor, AND Gate in TTL, 100 Gate ALU, 1000 Gate ULA, 10000 Gate Asic, .... FPGA, 1B+ gate CPU, etc)

asciilifeform: correct. so, proposing to put 64-state statemachine on each pin and look for it? and what, slip the timings so dram loses bits ? this is in the 'smoke' category, logic analyzer will find the peculiar defect, and victim buys another fpga.

OriansJ: Let us just assume the FPGA was not compromised and leverage it for the bootstrap work at this stage (I'll be going to pure LibreSilicon before I am finished but hey to each their own) ☟︎

asciilifeform: OriansJ: if i'm baking e.g. dram refresher -- then quite easily (and very frustratingly, in actual practice did, it is why it is ~impossible to bake a decent dram controller from scratch using fpga that hasn't been 'solved' ice40-style )

asciilifeform: the irons that speak these 'common patterns' -- already sabotaged decade+ ago, no need even to concern with fpga..

asciilifeform: the puzzler concerns 'general purpose' sabotaged fpga, rather than case where you know what the victim intends to connect and what protocols etc ☟︎

a111: Logged on 2019-04-06 21:51 asciilifeform: http://btcbase.org/log/2019-04-05#1907037 << i recommend to read the logs re 'specificity' ( picture yourself baking a sabotaged fpga , for victim whose gate net you do not know in advance. what would you put in it ? )

asciilifeform: http://btcbase.org/log/2019-04-06#1907066 << people who demand oddball instructions, can simply write own fpga payload and go happily on own path -- what am i missing ? ☝︎

asciilifeform: http://btcbase.org/log/2019-04-05#1907037 << i recommend to read the logs re 'specificity' ( picture yourself baking a sabotaged fpga , for victim whose gate net you do not know in advance. what would you put in it ? ) ☝︎☟︎

OriansJ: well, I guess a really important question to ask is at what level of lithography people here actually have trust? (1 transistor, AND Gate in TTL, 100 Gate ALU, 1000 Gate ULA, 10000 Gate Asic, .... FPGA, 1B+ gate CPU, etc) ☟︎☟︎☟︎

asciilifeform: ( incidentally, 'can redefine cpu instructions in boot rom for custom kompyooting' dun require fpga etc. fancy modern tech, e.g. dec alpha had it )

asciilifeform: http://btcbase.org/log/2019-03-10#1901148 << imho the ( ~homogeneous~ variant of ) fpga is actually the correct model. i.e. you get to stitch it later into however many parallel mechanisms you happen to need on a given occasion. ☝︎

asciilifeform: http://btcbase.org/log/2019-03-10#1901142 << programmable interconnect fabric ( similar to what's sold as fpga ) . iirc i detailed this in old thrd. ☝︎

asciilifeform: if it were possible to source an antifuse fpga for the http://btcbase.org/patches/fg-genesis/tree/fg.v , thing would be trooly indestructible short of incinerator or train running over it

asciilifeform: 1 annoying aspect of 'iron ffa'-gedankenexperiment, is that none of the available fpga ( either 'ice40' series, or the evil ones ) are anywhere near big enuff to prototype with. it'd have to be simulated a la http://www.loper-os.org/?p=2593 , slowly, and then straight to silicon.

asciilifeform: ( and no it aint in 'ent' or 'diehard' or in afaik any pc rng tester, it moar or less demands fpga )

asciilifeform: mircea_popescu: if we live to bake the fpga router thing, will be interesting to give it a ring buffer that'll hold coupla 100MB of frames, and dump'em to flash upon any unsanctioned reboot of attached irons.

mircea_popescu: phf pre-symbolics the "theorems" were "how do i computer" in general. those guys weren't playing around with custom fpga in their garage that they failed to sell. they were basically figuring out how to build a von neumann machine that can do things, which they did

asciilifeform: sorta whole orig thrust behind asciilifeform's archaeologies, experiments in old days, fpga room, etc

asciilifeform: BingoBoingo: the 'export ban' list is a hilarious read. ~nothing is ever removed from it, most of the thing was written in '80s-90s, and contains such items as fpga (afaik none are made in usa or have ever been, but somehow this dun stop the clowns) , and in practice seems to be used as 'lettre de cachet' against undesirables.

asciilifeform: which means yes, working with yet-other people who shoot from hip and have baked fpga.

phf: actually i'm not sure i said it in the logs, so my bad. i want a fully operational bolix fpga, or in the future other type of replica, complete with genera sources and other such bells and whistles

asciilifeform: phf: i'ma defo refer to the emulator when baking fpga clone, it has plenty of useful info re the instruction set

asciilifeform: and that actel, it's a 1200 gate antifuse fpga (well, without the 'f', lol), turns out.

asciilifeform: all of'em have inscriptions of the form DDDDDD-A/B, aside from the fpga (has just the #), and the serialnum chip (cypress, and i'ma post full output from the knife+notebook when i post whole orchestra)

asciilifeform: turns out there's even an early fpga in'ere, approx same density as the one in FG. ( but good noose is, it handles the crapple bus)

phf: re dks and fpga, i'm also not sure that he has enough data, or if he even knows if he has enough, or if the "master" in question has enough. i'm starting to suspect that the reason nothing's moving forward is because it's an intellectual bezel, a cat that's alive only until observed

a111: Logged on 2018-10-19 01:04 asciilifeform: amberglint: when i went to his house 10y ago, offered to him to make fpga-ized 'ivory' , 'pro bono', if he'd only cough up with what. answr was approx 'can't , unless my master permits, and he wouldn't'

asciilifeform: and ~then~ ( and this is what we have, but su reversers did not ) you load the thing into a (fairly inexpensive) fpga and try functional tests.

a111: Logged on 2018-11-16 02:52 asciilifeform: tldr : heathen altcoin hash algo which supposedly 'memory hard', but then you look and it only wants 2MB ( and possibly less, with optimizations) -- evidently so that fluffypony or watshisname could use ~his~ seekrit fpga..

asciilifeform: as i see it, it's damn near proof that the shitcoin 'exchange rates' are works of fiction -- 'if this is actually sellable for bitcent/ea., where is fpga ? '

asciilifeform: considering that even coupla watt worth of fpga outweighs coupla thou. js-eaters, in general

a111: Logged on 2018-11-11 00:05 asciilifeform: mircea_popescu: re 'bigendian box' -- i invested in one of them 'asic emulator' mega-fpga thingies, it so happens to come with 2 ppc cores on board, can double as bigendism test system.

asciilifeform: ( it so happens that asciilifeform knows that fpga with 2MB sram became available just as that thing was written )

asciilifeform: tldr : heathen altcoin hash algo which supposedly 'memory hard', but then you look and it only wants 2MB ( and possibly less, with optimizations) -- evidently so that fluffypony or watshisname could use ~his~ seekrit fpga.. ☟︎

a111: Logged on 2017-11-16 17:41 asciilifeform: moar concretely they go around propagandizing that if you build a fpga board you gotta use it, because 'mips is patented' ( in what country ? even in usa patent is 25y ) or 'risc-v is simplest' ( uh, nope ) and other idiocy.

asciilifeform: mircea_popescu: re 'bigendian box' -- i invested in one of them 'asic emulator' mega-fpga thingies, it so happens to come with 2 ppc cores on board, can double as bigendism test system. ☟︎

asciilifeform: ( the promisetronics with 'difficult to read with microscope, believe!11' thing is, as i gather, for the various folx in the biz of loading $circuit into fpga and selling 'as asic' , it isn't of great interest to asciilifeform in particular )

mircea_popescu: "The complexity of ASIC and FPGA designs has meant an increase in the number of specialist design consultants with specific tools and with their own libraries of macro and mega cells written in either VHDL or Verilog. As a result, it is important that designers know both VHDL and Verilog and that EDA tools vendors provide tools that provide an environment allowing both languages to be used in unison."

asciilifeform: apropos of upstack -- last wk asciilifeform did the ~yearly dig re 'does anyone actually sell fpga big enuff to demo 8192b-arithmetizer inside, fully unrolled' and turns out that yes (as of 6mo ago)

a111: Logged on 2018-10-25 15:44 mircea_popescu: now, a 4096 bit native fpga, specifically for rsa-ing and rsa-likes-ing, THAT might be very useful, because there the s-o-d item is major win.

asciilifeform: i have a 'i want to find out what it loox like in algebraic form , let's fpga it'

asciilifeform: washington can pay for its own auto-pill fpga, if they want one tho, i dun see why to do this work for them.

deedbot: http://www.loper-os.org/?p=2593 << Loper OS - Can the Serpent Cipher fit in the ICE40 FPGA?

asciilifeform: ( it is not meaningful to speak of 'bitness' of fpga per se, it's just a bag of blocks, typically 4-6bit LUTs plus some arithmetizers )

asciilifeform: funnily enuff i dun know of a single commercial/heathendom fpga that could house something of this size.

asciilifeform: faux-fpga-worx aint exactly the most fashionable scamolas, we're looking at obscure, vs 'sexy', frauds.

asciilifeform: presently i have nfi whether this is physically possible, or how in particular -- could be fpga-like device where somehow the components actually ~move~ into position ; or sumthing where you can optically burn away the unused tracks through 'window' ; or some yet entirely unknown trick.