500+ entries in 0.234s
a111: Logged on 2019-04-17 19:26 asciilifeform: in principle it would be trivial to bake a standardized, commoditized
fpga. the 'gowin' people could have easily done this, an' published the interconnect scheme and the delay map. BUT what no one knows how to do, is to make this a +ev proposition. observe, the chinese had no interest in trying to commoditize , but instead went 'we'll do exactly what xilinx does but slightly cheaper , out of chinesium'
a111: Logged on 2015-03-24 18:38 ascii_field: mats: the way the story normally ends is that the reversed
fpga becomes quasi-usable nearly the same time it goes out of print and replaced with incompatible version...
a111: Logged on 2019-04-12 15:51 asciilifeform: to briefly revisit ~earthling~ gedanken-
fpga tho : it is by no means obv. that the arity has to be 4. anyffin you can tile the 2d plane with, is a legit arity. ( and if you permit 2 or moar types of tile -- then even moar possible options. )
a111: Logged on 2019-04-12 14:46 asciilifeform:
http://btcbase.org/log/2019-04-12#1908318 << dun confuse the gedanken-
fpga lut thrd with the 'ideal alu bus' one. i.e. a 64-bit bus is a set of 64 wires ; a 64-bit ~lut~ otoh is 2^64 sram cells , a planet-sized object , and with 1 lonely flipflop , lol, somewhere inside its molten core
mp_en_viaje: now imagine a
fpga, surrounded by 725 islands, leveraging each one thing, this is net-a that is tcp-ip-b, that'
mp_en_viaje: so : suppose a) tcp/ip is intrinsically, by its very [deliberate, and previously uknown-ly so] design vulnerable to "blowhammer", which is a class of yet undescribed attacks ; suppose your
fpga includes an electrically-isolated leverage for a.
a111: Logged on 2019-04-06 23:35 OriansJ: Let us just assume the
FPGA was not compromised and leverage it for the bootstrap work at this stage (I'll be going to pure LibreSilicon before I am finished but hey to each their own)
a111: Logged on 2019-04-06 23:26 asciilifeform: the puzzler concerns 'general purpose' sabotaged
fpga, rather than case where you know what the victim intends to connect and what protocols etc
a111: Logged on 2019-04-05 23:25 OriansJ: well, I guess a really important question to ask is at what level of lithography people here actually have trust? (1 transistor, AND Gate in TTL, 100 Gate ALU, 1000 Gate ULA, 10000 Gate Asic, ....
FPGA, 1B+ gate CPU, etc)
OriansJ: Let us just assume the
FPGA was not compromised and leverage it for the bootstrap work at this stage (I'll be going to pure LibreSilicon before I am finished but hey to each their own)
☟︎ a111: Logged on 2019-04-06 21:51 asciilifeform:
http://btcbase.org/log/2019-04-05#1907037 << i recommend to read the logs re 'specificity' ( picture yourself baking a sabotaged
fpga , for victim whose gate net you do not know in advance. what would you put in it ? )
a111: Logged on 2019-04-05 23:25 OriansJ: well, I guess a really important question to ask is at what level of lithography people here actually have trust? (1 transistor, AND Gate in TTL, 100 Gate ALU, 1000 Gate ULA, 10000 Gate Asic, ....
FPGA, 1B+ gate CPU, etc)
a111: Logged on 2019-04-05 23:25 OriansJ: well, I guess a really important question to ask is at what level of lithography people here actually have trust? (1 transistor, AND Gate in TTL, 100 Gate ALU, 1000 Gate ULA, 10000 Gate Asic, ....
FPGA, 1B+ gate CPU, etc)
OriansJ: well, I guess a really important question to ask is at what level of lithography people here actually have trust? (1 transistor, AND Gate in TTL, 100 Gate ALU, 1000 Gate ULA, 10000 Gate Asic, ....
FPGA, 1B+ gate CPU, etc)
☟︎☟︎☟︎ mircea_popescu: phf pre-symbolics the "theorems" were "how do i computer" in general. those guys weren't playing around with custom
fpga in their garage that they failed to sell. they were basically figuring out how to build a von neumann machine that can do things, which they did
phf: actually i'm not sure i said it in the logs, so my bad. i want a fully operational bolix
fpga, or in the future other type of replica, complete with genera sources and other such bells and whistles
phf: re dks and
fpga, i'm also not sure that he has enough data, or if he even knows if he has enough, or if the "master" in question has enough. i'm starting to suspect that the reason nothing's moving forward is because it's an intellectual bezel, a cat that's alive only until observed
a111: Logged on 2018-10-19 01:04 asciilifeform: amberglint: when i went to his house 10y ago, offered to him to make
fpga-ized 'ivory' , 'pro bono', if he'd only cough up with what. answr was approx 'can't , unless my master permits, and he wouldn't'
a111: Logged on 2018-11-16 02:52 asciilifeform: tldr : heathen altcoin hash algo which supposedly 'memory hard', but then you look and it only wants 2MB ( and possibly less, with optimizations) -- evidently so that fluffypony or watshisname could use ~his~ seekrit
fpga..
a111: Logged on 2018-11-11 00:05 asciilifeform: mircea_popescu: re 'bigendian box' -- i invested in one of them 'asic emulator' mega-
fpga thingies, it so happens to come with 2 ppc cores on board, can double as bigendism test system.
a111: Logged on 2017-11-16 17:41 asciilifeform: moar concretely they go around propagandizing that if you build a
fpga board you gotta use it, because 'mips is patented' ( in what country ? even in usa patent is 25y ) or 'risc-v is simplest' ( uh, nope ) and other idiocy.
mircea_popescu: "The complexity of ASIC and
FPGA designs has meant an increase in the number of specialist design consultants with specific tools and with their own libraries of macro and mega cells written in either VHDL or Verilog. As a result, it is important that designers know both VHDL and Verilog and that EDA tools vendors provide tools that provide an environment allowing both languages to be used in unison."
a111: Logged on 2018-10-25 15:44 mircea_popescu: now, a 4096 bit native
fpga, specifically for rsa-ing and rsa-likes-ing, THAT might be very useful, because there the s-o-d item is major win.