log☇︎
51 entries in 0.614s
asciilifeform: i.e. yer still stuck with their closed shitware, and with closed 'ip cores' (libraries) from them if you want sdram, ethernet, etc.
asciilifeform: thing needs to eat packets, parse fields, sort'em into tables, parallelize lookups ( and below all of this, do such things as driving the sdram , the nic PHYs , shuttle data b/w processors )
asciilifeform: ( before anybody asks -- imho it is physically impossible to get this effect on pc iron, where not only caching but such things as sdram burst r/w exist )
mircea_popescu: double bit detect single bit correct 144bit ddr3 sdram.
asciilifeform: but nobody could be arsed to mount it with sdram socket and gb nic magnetics ?!
asciilifeform: ever take close look at board with sdram ? needs equal paths ( the wiggling lines you see are called 'meanders' )
asciilifeform: upstack : in case it wasn't obvious : it is possible to make ddr2 sdram controller , nic, etc.
asciilifeform: incl. at least 1 fella who hit the famous ddr-sdram wall.
asciilifeform: as it is, even crapple pocket comps have standalone sdram.
asciilifeform: ( re pc vivisection : one item on asciilifeform's wish list, that does not currently exist : a doctored stick of sdram that can be read/written 'out of band', i.e. via another hole )
asciilifeform: xilinx + sdram + usb20tron inside.
asciilifeform: anyway the badnoose for mircea_popescu is that you're stuck with the busy signal because that's what the 's' in sram or sdram stands for. the synchronicity.
asciilifeform: dun get quite so hot an' bothered, it's still made of traditional xilinx (which needs the massive toolchain) and still contains sdram ( for which no controller other than xilinx's , works ) but this board is actually useful -- in comparison with my existing aging 'ml501' ( as pictured in http://www.loper-os.org/?p=702 , http://www.loper-os.org/?p=797 )
asciilifeform: and unlike, e.g., most sun boxes, they have normal 'earthling' pci, and reasonably obtainable sdram.
asciilifeform: check out how sdram works some time.
asciilifeform: sdram was not, unfortunately, the only device in the shitlist either.
mircea_popescu: asciilifeform it doesn't HAVE to use sdram though does it.
a111: 26 results for "sdram", http://btcbase.org/log-search?q=sdram
asciilifeform: $s sdram
asciilifeform: i wish this were not so, but so far afaik the set of folks who understand everything from galois theory to O(..) runtimes to sdram bus timings includes 1) mircea_popescu 2) asciilifeform .
assbot: Logged on 21-10-2015 15:06:41; asciilifeform: sounds appealing. what does a 4GB SDRAM stick cost there ?
asciilifeform: sounds appealing. what does a 4GB SDRAM stick cost there ? ☟︎
ascii_field: and if you want, e.g., a 100BaseT nic, or sdram controller, it has to be laid out mainly by hand using floor plan of the particular chip and explicit coordinates. which vendor can do, and you (user) cannot.
asciilifeform: you ~can~ sloppily 'bit-bang' a 10BaseT ethernet nic. but ~not~ sdram controller.
asciilifeform: sdram is the absolute worst case, because the difference between 'acceptable performance' and 'works at all, for any purpose' is slim
assbot: Logged on 17-06-2015 11:55:10; kakobrekla: http://log.bitcoin-assets.com/?date=10-10-2014#867175 < http://opencores.com/project,ddr2_sdram what am i missing here ?
assbot: DDR2 SDRAM Controller :: Overview :: OpenCores ... ( http://bit.ly/1CdnmDl )
kakobrekla: http://log.bitcoin-assets.com/?date=10-10-2014#867175 < http://opencores.com/project,ddr2_sdram what am i missing here ? ☝︎☟︎
assbot: Logged on 29-05-2015 13:39:18; asciilifeform: http://log.bitcoin-assets.com/?date=29-05-2015#1147596 << laugh, but it isn't so hard if you are emulating ordinary sdram. if one side issues a write cycle, the other gets a wait-state signal (gets to think that the dram is in refresh state)
asciilifeform: http://log.bitcoin-assets.com/?date=29-05-2015#1147596 << laugh, but it isn't so hard if you are emulating ordinary sdram. if one side issues a write cycle, the other gets a wait-state signal (gets to think that the dram is in refresh state) ☝︎☟︎
asciilifeform: there was an outfit which sold something quite like this (fpga on sdram stick) and even one in the shape of a cpu, which could sit down in ordinary cpu socket on multisocket mb
asciilifeform: (connection via ram slots is not, as it may appear, lunacy, but could be done with fpga, which would pretend to be a slice of sdram to two boxes at the same time, ignoring refresh cycles and managing locking somehow)
asciilifeform: x86 never runs from rom. not even on warmup when sdram waitstate timer is not yet initialized
asciilifeform: most of the ones i've purchased and cut open thus far have very similar 8 to 16-bit wide sdram (ddr2 typically) - almost always 'hynix' or samsung
assbot: 14 results for 'sdram' : http://s.b-a.link/?q=sdram
ascii_field: !s sdram
ascii_field: now bringing things back to my original boojum - you can't drive sdram with 74xxxx ttl.
assbot: 5 results for 'sdram controller' : http://s.b-a.link/?q=sdram+controller
ascii_modem: !s sdram controller
asciilifeform: you can read an sdram spec by, e.g., 'micron' (i did) and implement a ddr2 sdram controller.
asciilifeform: or sdram controllers
asciilifeform: sometimes N or more paths have to be of the same length (to 0.1 mm or so) and you end with 'meanders' (look at the bottom side of stick of sdram)
asciilifeform: e.g. support PCI or die, support consumer SDRAM sticks or die, etc.
asciilifeform: to understand 'burst', see any sdram datasheet, e.g. http://download.micron.com/pdf/datasheets/dram/sdram/512MbSDRAM.pdf
asciilifeform: if you don't optimize for a particular fpga, you can't get anything close to the maximum rated clock of the sdram in question
asciilifeform: take, for instance, sdram controllers
asciilifeform: or hell, even fpga with sdram controller
asciilifeform: Luke-Jr: sdram plus fpga which does nothing but sCrypt, vs. a general-purpose pc?
Luke-Jr: asciilifeform: the goal of memoryhard is that it the SDRAM would perform equally well with any host
asciilifeform: everybody knows that you can get FPGA+sdram socket boards for pocket change, right?
asciilifeform: it just needs a different ASIC (one that includes an SDRAM controller.)