log☇︎
13 entries in 0.741s
a111: 11 results for "riscv", http://btcbase.org/log-search?q=riscv
asciilifeform: !#s riscv
a111: Logged on 2018-06-11 20:57 asciilifeform: fuck riscv. it was deliberately designed with no arithmetical carry, to cripple cryptography.
asciilifeform: fuck riscv. it was deliberately designed with no arithmetical carry, to cripple cryptography. ☟︎
a111: 7 results for "riscv", http://btcbase.org/log-search?q=riscv
asciilifeform: !#s riscv
asciilifeform: i fucking hate riscv
swiftgeek: would be nice to have nicer implementation with riscv :D
a111: 3 results for "riscv", http://btcbase.org/log-search?q=riscv
asciilifeform: !#s riscv
asciilifeform: riscv is a turd
asciilifeform: so it's a first-class wrecking. sorta like what llvm used to be prior to apple crowning it. riscv is waiting for its apple.
mircea_popescu: "=== RISCV === While this architecture is extremely limited in performance, price, and performance per watt compared to x86, ARM, or POWER, it is also one of the only fully open source CPU architectures available outside of an FPGA. and may eventually be competitive with MIPS in terms of raw performance. Currently there are no RISCV SoCs in production, however projects such as lowRISC aim to change that: http://www.lowrisc.