asciilifeform: 'they hoped for "a new spire that is adapted to the techniques and the challenges of our era"' << lol!!
asciilifeform did , repeatedly, write, and many yrs ago nao, that the 'reverse fpga' people are solving the wrong problem -- by the time they achieve anyffin, vendor simply replaces the design and laffs
asciilifeform: ( my current understanding, is that it would be actually ~cheaper~ to bake own homogeneous-fpga thing ... )
asciilifeform: he didn't conjure up the delay map, but asciilifeform neither knows how to do this without seven figures' worth of microscopy
asciilifeform: mp_en_viaje: knowing 0 aside from the product , i would say it is not correct to put wolf in the company of koch -- wolf actually did sumthing nontrivial and useful ( mapped out the ice40 matrix )
asciilifeform: ( the '18 one , i have, and worx for low-frequency applications like e.g. 'fg 2' , but that's pretty much it )
asciilifeform: mp_en_viaje: (as you can read further downthread) the misfortunate thing is that died before got anywhere near mature ice40 tool.
asciilifeform: mp_en_viaje: 6mo old page. i think he already bent.
asciilifeform: i have nfi either way. ( in fact had nfi that he ~had~ a piggy )
asciilifeform: mp_en_viaje: re 'what happened there' , d00d seems to say his piggy went dry.
asciilifeform: i use'em the way folx on submarine use their pics of trees an' birds etc
asciilifeform: BingoBoingo: i take the pics mostly for self, to occasionally look at and remember that there ~is~ an outside☟︎
asciilifeform: walking across europistan isn't a mp_en_viaje-strictly activity because expensive. but because takes time.
asciilifeform: and pics are great, i suspect most of these 'everythings' i will only see if mp_en_viaje finds time to make a pic of'em.
asciilifeform: iirc already posted 1 , with the wine glasses
asciilifeform: if asciilifeform could leave the idjit reservation for even say whole 6 wks, perhaps effect would wear off. but when or how would this even happen lol.
asciilifeform doesn't post much travel photo on acct of... it'd be like a dog posting food pics. 'omfg errything here was Built By People! and not josephsmiths! omfg have you seen a light post like this?' etc
asciilifeform: hey picture how crowded would be if erryone were somehow mp_en_viaje
asciilifeform salivates at the thought of seeing e.g. budapest, but presently having to save up 'vacation' juice for BingoBoingostan expeditions, rotting in bed with flu, etc☟︎
asciilifeform: mp_en_viaje: 'where to walk to' is absolutely killer here in ameristan. asciilifeform walks erry day, but frustratingly in (however large) circles
asciilifeform: diana_coman: re 'Natural' type -- this is one of asciilifeform's persistent headaches -- the lang forces certain things to be indexed by 'Natural', and i optimized for minimal # of casts ( i fucking hate casts, and imho the fact that one cannot write a proggy ENTIRELY without'em, is a language bug )
asciilifeform: afaik ~all of europistan walkable, except maybe bucharest where they do the orc thing of 'we'll all buy merc on credit and park on sidewalk'
asciilifeform: i settled it in favour of having preconds etc. on the ~user-operable~ api ( as pictured in ch11. )
asciilifeform: e.g. one ~could~ have preconds on ~all~ of the ops, but then say goodbye to inlining and hello to 'geological' rsa.
asciilifeform: there's an engineering tension b/w 'maximally consistent' and 'performs reasonably on pc' , which i resolved mostly but not entirely in favour of the former
asciilifeform: 'MachineBitnessLog2' is prolly the most obv. example of this, it only comes into play in ch13
asciilifeform: tho i do suspect that i did introduce certain knobs before there was strictly a need to do so, solely on acct of imperfect plan ( recall, most of the proggy through ch10 or so, pre-existed the start of the human-readable series )
asciilifeform: ( which is admittedly annoying, from notational purism pov, but not much to be done about it )
asciilifeform: if it's re the arrays, these are forced into 0 .. N notation by the lang
asciilifeform: diana_coman: i'm still stumped re where it was that i had 'most junior bits on the left' tho☟︎
asciilifeform: re shift_right and shift_left -- these follow the machine convention, which afaik has been unchanged since 1960s and long pre-dates 'endianism' wank
asciilifeform: diana_coman: re the stylistic nitpicks : there'll defo be a tail-end ch where various items get moar descriptive names. and i agree with diana_coman's pt re e.g. 'Get_Head'
asciilifeform: mod6 ^ + other ffa-eating folx, i suspect will find diana_coman's piece quite handy☟︎
asciilifeform: it's the most massively centralized industry that exists. there are actually moar independent satellite launchers than e.g. <= 70nm fabs.
asciilifeform: BingoBoingo: there aint any 'small shops' in chip biz.
asciilifeform: asic is a high enuff risk biz that the people who do it, are conservative to the point of 'if this exact thing hasn't been done before, fughetaboutit'☟︎
asciilifeform: observe that even the btc asic thing was financed by outright fraud (and on massive scale)
asciilifeform: ( tho iirc there was an actual attempt to organize 1, they launched a crate or 2 of fist-sized beepbeeps into deliberately burns-in-coupla-months orbit )
asciilifeform: sorta why there aint a 'open sores satellite launcher' firm, etc
asciilifeform: ( and, bonus, their shitware aint even sold outside of ru )
asciilifeform: 2y ago asciilifeform found a ru firm that cloned altera's larger fpga. they do SAME THING
asciilifeform: the entire biz model of fpga market as it existed since 1990 or so, is based specifically on pulling this kinda scam.
asciilifeform: cuz they dun give you the info that you'd need to actually bake the config streams for these 'from 1st principle'.
asciilifeform: i.e. yer still stuck with their closed shitware, and with closed 'ip cores' (libraries) from them if you want sdram, ethernet, etc.
asciilifeform: in principle it would be trivial to bake a standardized, commoditized fpga. the 'gowin' people could have easily done this, an' published the interconnect scheme and the delay map. BUT what no one knows how to do, is to make this a +ev proposition. observe, the chinese had no interest in trying to commoditize , but instead went 'we'll do exactly what xilinx does but slightly cheaper , out of chinesium'☟︎
asciilifeform: it's a 1st-class bitch to do this with 0 cooperation from the folx who make the chip, mainly cuz erry single revision has different intrinsic delays.
asciilifeform: the ice40 people , arguably 'solved half of the problem' -- they found a reasonably homogeneous chip so that they could describe the actual connections. but apparently were unable to map out the delays.
asciilifeform: but if you want deterministic paths, currently yer stuck using the vendor shitware. ( what's worse, even on ye olde xilinx apparently it is impossible to write e.g. a working 200MHz+ dram controller from 1st principles, yer forced to use the vendor's shitware that actually knows the gate delays, to equalize the paths )
asciilifeform: bvt: naturally synth tool cannot 'squeeze blood from a stone'
asciilifeform: ( it will not only occupy the ~entire matrix, even if you somehow get it to fit; but also won't meet timing spec, even at pretty modest clock )
asciilifeform: as it stands, it is just about impossible, presently, to bake even very simple dram controller for ice40
asciilifeform: this is why fpga design ~never runs at anywhere near the max switching rate specced by the device vendor. a good synth tool 1) tries to minimize the delays 2) gives you an accurate figure for max clock, and for propagations of individual paths ( if you have e.g. dram hanging off the thing, these are critical )
asciilifeform: bvt: re delays, it's a quite basic fact, if you have e.g. nand gate in 1 path, and straight wire in other, the signals will get to other side at different times
asciilifeform: bvt: thing was 'work in progress' for years iirc.
asciilifeform: ( ~why~ went nowhere -- i do not presently know; it may be simply from lack of time , ~or~ could easily be because he does not in fact have the relevant gate-delay numbers . the published docs suggest the latter as possibility )
asciilifeform: he had plan to dig into the larger fpga from same vendor, and to improve the synth engine, but apparently went nowhere.
asciilifeform: bvt: i'm satisfied that wolf properly described the low-level fabric of the 8k model. but the synthesis engine is pretty barbaric.
asciilifeform suspects that this would require finding some other planet to sell'em on..
asciilifeform: evidently, the hero who knows how to turn work on sane kompyooting irons/softs into a self-sustaining economic item, is not yet born.
asciilifeform: aand last update on the ice40 page seems to be 30 jan '18. so nuffin happened there since i 1st found it. ( there was, at one point, e.g. talk of support for the larger lattice co. chips )
asciilifeform: re wolf, i admit to being surprised that he found any kinda moneys at all
asciilifeform: meanwhile, in february, chinese 'gowin semiconductor co' cloned ice40. but if anyone thought this means 'open spec', guess again, only worx with their 'YunYuan' closed shitware toolchain.☟︎
asciilifeform: from, near as i can tell, starvation.
