log☇︎
11 entries in 0.437s
asciilifeform: typically gate wedged into metastability . difficult to calculate tho.
asciilifeform: let's take from other end of digestive tract. consider 1 AND gate. idealized, no metastability, no breakdown voltages, literally 'ands' two logical values. ( can have physically limited to % of c speed, if you like, but this is uninportant )
asciilifeform: funny bit re metastability -- i did not realize that it was the one and only possible culprit until i confirmed that the logic analyzer in fact saw, on multiple occasions (at least 1 ppm) a variant logic state from what the rest of the circuit saw.
a111: 6 results for "metastability", http://btcbase.org/log-search?q=metastability
asciilifeform: !#s metastability
asciilifeform: it lets you have asynchronous circuits without metastability problems
decimation: re: metastability https://filebox.ece.vt.edu/~athanas/4514/ledadoc/html/pol_cdc.html
asciilifeform: against metastability?
mircea_popescu: asciilifeform i think i may prove a metastability re neutronsa
asciilifeform: metastability problem is solved by every gate having a 'inputs are ready' signal as well as inputs
BTC-Mining: He'll accidentally provoke a vacuum metastability event, resulting in a stabler state propagating throughout the Universe at the speed of light, defining new constants for the laws of physics, rendering all Earth and its matter... different.