asciilifeform: they prototype on ordinary, sram-based one, then pay to have it metallized.

asciilifeform: mircea_popescu: this is actually how existing ic industry worx, a good half of the 'asics' are actually 'hard copy fpga', recall the early miner derps threads.

asciilifeform: there's no 'bitness' in fpga, it's a bag of gates, if you have enuff of them you can made n-bit addder, divider, whatever one likes

asciilifeform: what's the 'crutch' ? not spending a $3mil + 1yr delay if there's bug in layout , like 1970s folx had to ?

asciilifeform: the other is political, all of the existing vendors obfuscate and keep seekrit the necessary docs to actually program the thing. ice40 happens to have been reversed, but it is ruinously small ( still ~150x bigger than the miniature xilinx i baked FG from, however , but too small even for 4096bit adder )

asciilifeform: there's 2 well-known minuses. 1 is that yer making circuit out of immovable parts, connected by drawing line though multiple elements ( bus lines are generally few ) , this gives you much slower circuit with many fewer logical elements than if you had made the device physically from scratch .

asciilifeform: ( orig ancestor was the PAL. there were PALs in yer ro 'spectrum' clone. )

asciilifeform: thing's existed since mid-80s, the pluses and minuses of it are well-documented

asciilifeform: i disagree -- fpga is analogous to gutenberg's movable type; classical 'asic per design' to chinese whole-plate.

asciilifeform: mircea_popescu: for design that actually fits inside, you end with exactly 'slow asic', with the added win that it's a homogeneous object with no e.g. 'and here is where he will rsa and here is where the low bit of multiplier will live' sabotage target available to enemy mole in vendor plant.

asciilifeform: buncha gates, as many as can fit, and a programmable switching matrix, a la old telco , look up tables made of 4-6 bits of sram that turn a given unit into 'and' , 'or', 'xor', half-adder, straight wire, whichever is necessary. i dun know how to more rigorously define, it is one of the simplest devices, straight homogeneous grid of sram cells plus a couple hundred (thousand, in larger devices) 'express lanes' made of straight metal,

asciilifeform: for that matter current FG is baked on fpga, from evil old xilinx.

asciilifeform: and pretty much the ideal 'nonspecificity of diddling' platform, it is quite impossible to meaningfully boobytrap fpga fabric if you don't have foreknowledge of what will go into it and precisely where.

asciilifeform: why not ? it's the simplest item, and theoretically the others can be made from it.

asciilifeform: mircea_popescu: i've outlined several items, historically. will summarize for the l0gz, in order of descending ( per asciilifeform's lights ) universality : 1) sane fpga 2) sane minimal cpu 3) 8192-bit arithmetizer ( a la ye olde weitek! but for ints ) 4) 2+3 , if somehow can be fit into 1 die 5) 1chip carrierless radio ( per thread ) 6) sane ethernet controller .

asciilifeform: mircea_popescu: let's suppose we make the req'd contact. what wouldja want to fab 1st ?

asciilifeform: ( and mircea_popescu seems to concur with my verdict, they're ripoffs )

asciilifeform: it's sorta like the outfit we had FG pcb baked in, but moar extreme.

asciilifeform: i expect they use meat hands, with microscopes, to package.

asciilifeform: http://btcbase.org/log/2018-10-25#1865831 << it's a hand-cranked 'for small runs' shop, 1 of 2 known to exist. hence the riotous per-unit pricings. ☝︎

asciilifeform: http://btcbase.org/log/2018-10-25#1865790 << i sat for 2h last night reading 'standard' and 'rationale', and was not able to determine ! will require extensive dig into the gnat src, i suspect. ☝︎

asciilifeform: the other thing i oughta mention, is the amt of sweat required. if asciilifeform were a free man, could do it in perhaps a year. but at present-day capacity, would not dare to even try.

asciilifeform: which is not so bad, quite enuff for a mips ( or even the old bolix , supposing anyone had the layout for it ) but laughably small for e.g. fpga.

asciilifeform: ( ~300k transistor )

asciilifeform: per my reckoning, you can ~maybe~ fit a '386' in these.

asciilifeform: sooo taking only the lower bounds ( 4mm^2 ; 700 eu. per mm^2 ; 30 eu. per tin can ) and not counting eu fees / taxes / exorbitant shipping couriers , and assuming 25 , we end up with a figure of 3550 eu, 'old toyota' gets you 25 units, some of which may even work...

asciilifeform: nao multiply it all by 2 or 3, because that's how many shots it usually takes to properly polish off ic product.

asciilifeform: ( if yer baking cpu, or fpga, or other item large enuff to make the game worth the candles )

asciilifeform: plus 'shipping and eu export fees'. but the other big hit is packaging cost : 30 - 100 eu. ~per chip~, depending on # of contacts / shape of can. ☟︎

asciilifeform: here's what i was able to find , via the pdf turd : base charge is 700 -- 12000 euro / mm^2 , depending on density ( 0.35uM to 28nm ); this gets you 25 ~bare~ dies , + 'phree 15 if available' ;

asciilifeform: ( the other sub-$1mil fab is mosis co., but it is in usa, serves primarily usg, and dun publish prices, in the past i tried to get estimate from it but without success )

asciilifeform: http://btcbase.org/log/2018-10-25#1865758 << imho worth linking to the prev thread : http://btcbase.org/log/2016-12-08#1579598 ☝︎☝︎

asciilifeform: ssd wear is a thing. ☟︎

asciilifeform: not to mention that even 'soldier' noad, is not actually cheap, costs like horse not like goat. ( considering that you want ssd, something like a respectable net pipe, uninterrupted current, distance from mordor, if available, etc )

asciilifeform: http://btcbase.org/log/2018-10-25#1865782 << dun matter if yer an admiral, or emperor, you got 1 arse. the node you ~generate~ tx on, ~is~ a battleship. ☝︎