log☇︎
13600+ entries in 0.004s
asciilifeform: Mocky: pretty sure mp described in great detail how his implementation worx
asciilifeform: wb Mocky
asciilifeform: if wants reaudition, can go an' beg in 2 separate l1 castles for reprieve.
asciilifeform: imho d00d had moar than longenuff to come to his senses.
asciilifeform: !!v 78592CA40FFF999DFE5BB08161B142C60307C8645EFFE82541EEC40ED40A719F
asciilifeform: !!rate OriansJ -1 read-only brain ☟︎
asciilifeform: ^ last , afaik, honest man in the field
asciilifeform: !#s henderson
asciilifeform: or if it dun exist, what the everliving fuck has erryone claiming to be involved in 'computer graphics' been doing since 1970s ? aside from eating own shit.
asciilifeform: where is it ?
asciilifeform: ooooor how about 1 that'll draw a http://www.loper-os.org/?p=2842#selection-716.0-718.2 , without also WHOLE DAY of hand-fiddle , and into a scalable-to-user's-terminal item, rather than bitmap garbage ?
asciilifeform: ^ spoiler : latex won't
asciilifeform: PeterL: fughet even the logic gates. where's the proggy that'll draw e.g. http://www.loper-os.org/?p=2875#selection-1129.0-1343.1 using strictly spec of the relative sizes of the items, and put the captions where they belong ? without WHOLE DAY of hand-fidgeting the coords to only then find that www browser turns it into soup when the moon is in the wrong phase.
asciilifeform: would be, if it didn't ask you to manually shit out the coordinates for each fucking line.
asciilifeform: i thought http://btcbase.org/log/2019-04-12#1908376 was pretty clear. ☝︎
asciilifeform: PeterL: it's the exact opposite of the kind of thing.
asciilifeform: progress!!!!!
asciilifeform: 'bbbut you can go and watch lolcat fucking 4 chix 1 with each paw, at 85 hertz! asciilifeform !'
asciilifeform: somehow in 1985 someone somewhere had comp that's an actual fucking tool for thought, and where could go p=and(x,y) q=or(x,p) r=and(p,q) and get a set of gates arranged in neat rows and with minimal-length non-intersecting wires between'em . and today not. ☟︎
asciilifeform: ftr the rectangles in ^above STILL not 100% of consistent requested size. cuz apparently you CANNOT do this with html. or svg. or anyffin else.
asciilifeform: 'you thought you could put little arrows from one place to another in'em without hand-diddling coordinates for each one ?' ☟︎☟︎
asciilifeform: 'oh very funny asciilifeform , you thought modern comp could be programmed to shit out logically-defined rectangles with readable text ?'
asciilifeform: WHY?
asciilifeform: i'm not even raging on acct of 'draw gedanken-fpga', it can happily live for another year without being drawn. but i had to spend fucking MONTH hand-sweating out http://www.loper-os.org/?p=2875 , and similar
asciilifeform: it's a geometric device. and yes, can be explained in text, or in morse code, etc. but really belongs as a manipulable graphic, if you already fucking have a comp that displays these ( or wtf is it for, for lolcats ?! )
asciilifeform: exhausted the (veery generous) 1h time budget i gave to this problem, and with exactly 0 to show for it.
asciilifeform: liquishit.
asciilifeform: believe or not, i powered up a winblows toilet , and tried coupla 'free' offerings
asciilifeform: http://btcbase.org/log/2017-12-29#1760910 << thread from the ~previous~ time asciilifeform tried to do this kinda thing. ☝︎
asciilifeform: i have entire bookcase fulla dead tree where entirely readable logic diagrams and defo not produced in pen by hand.
asciilifeform: and sometime between then and nao, evaporated
asciilifeform: that capability was there in fucking 1972. ☟︎
asciilifeform: and the notion is esp. outrageous when sitting next to a comp, which theoretically ought to make this a three minute job.
asciilifeform: i aint drawing it with pen. and certainly not animating anyffin in pen, i aint walt disney.
asciilifeform: is
asciilifeform: $item is just slightly too large to draw with pen in reasonable time ( and with asciilifeform's penmanship ) ; but precisely small enuff to be a++ 'animated gif' didacticism -- if, that is, the opensores people actually spent past 20y writing usable soft rather than eating own shit
asciilifeform: hair-pulling level of pervasive idiocy. ☟︎
asciilifeform: meanwhile, in loathesome shitware : asciilifeform when woke up thought, 'i'ma quickly draw the gedanken-mechanism for mp' . went then 'with what ?' -- turns out, erry single didactic digital logic drawing thing, run in either java, or winliquishit, or is opensores linuxturd that builds but then displays blank page, or similar...
asciilifeform: PeterL: iirc you were a chemist -- recall the 2d crystal spacegroups
asciilifeform: PeterL: dun even need 3d cube -- hexagon on 2d plane worx same for ^
asciilifeform: http://xahlee.info/Wallpaper_dir/c5_17WallpaperGroups.html << handy ref/likbez re subj.
asciilifeform: to briefly revisit ~earthling~ gedanken-fpga tho : it is by no means obv. that the arity has to be 4. anyffin you can tile the 2d plane with, is a legit arity. ( and if you permit 2 or moar types of tile -- then even moar possible options. ) ☟︎
asciilifeform: ^ astro puzzle : calculate the minimal propagation delay in this 'fpga'. ( just how close can one park a jupiter to another before they merge.. etc )
asciilifeform: this gets even lulzier tho -- each bit in a lut is there because it connects to a neighbour (e.g. in the 4bit example from earlier thread -- 4 neighbours ) . nao picture the galaxy of 'neighbours' for the 64bit item...
asciilifeform: http://btcbase.org/log/2019-04-12#1908318 << dun confuse the gedanken-fpga lut thrd with the 'ideal alu bus' one. i.e. a 64-bit bus is a set of 64 wires ; a 64-bit ~lut~ otoh is 2^64 sram cells , a planet-sized object , and with 1 lonely flipflop , lol, somewhere inside its molten core ☝︎☟︎
asciilifeform bbl:meat
asciilifeform: see also ye olde fable re the sultan's chessboard.
asciilifeform: ( by asciilifeform's napkin estimate, there are possibly 52 bits of addressable electric memory on planet3 atm.. ) ☟︎
asciilifeform: http://btcbase.org/log/2019-04-11#1908275 << this also howler btw. 64bit sram weighs approx. a jupiter... ☝︎
asciilifeform: ( picture, 1st fella to solve the exercises, gets prize, a sample fpga, lol )
asciilifeform confronts the fact that he's prolly doomed to pen a ffa-style vlsi tutorial 1 day..
asciilifeform: http://btcbase.org/log/2019-04-11#1908273 << i neglected to add to this: the wider the lut, also the slower ( why -- will leave as exercise, but it aint difficult to figure out ) ☝︎☟︎
asciilifeform: http://btcbase.org/log/2019-04-11#1908303 << for folx w/out the spare cycles to read the orig horror -- classical nsaware , complete with 'null ciphers' , 'negotiations', etc lulz ☝︎
asciilifeform bbl also : tea
asciilifeform: laters
asciilifeform: but i'll be the 1st to admit that i have not even the faintest clue of how could amortize . considering e.g. fg experience.
asciilifeform: ( and, just nao, no free hands )
asciilifeform: but currently no impetus.
asciilifeform: granted i ~could~ have heathens bake coupla hundred dies, for the cost of e.g. that bolix
asciilifeform: as i described in last yr's thrd, would 1st have to invent some -- even hypothetical -- means whereby +ev
asciilifeform: it aint as if i have a queue of folx at the door demanding clean fpga lol
asciilifeform: it's moar like moon launcher than desktop experiment.
asciilifeform: mp_en_viaje: you wouldn't want to even consider baking unless ~very~ concrete idea of what (and simulated the thing)
asciilifeform: like the solar panel people do.
asciilifeform: ~then~ can bake as large as dinner plate if feel like.
asciilifeform: a la old hdd.
asciilifeform: as illustrated in yest. thrd, 'many small lut' give you , among other things, a means of working around crystal defect.
asciilifeform: mp_en_viaje: this is prolly the #1 noob q of folx digging into subj. answr is yield, it is why 'pentium' isn't fist-sized
asciilifeform: sram is really the degenerate case, '1 giant lut'
asciilifeform: ( it reduces to an expensive sram )
asciilifeform: not much that can be done with this.
asciilifeform: so e.g. 64 would give you a die with, what, 8 luts. ☟︎
asciilifeform: mp_en_viaje: the sq.metrage of cell grows exponentially with bitness of lut ☟︎
asciilifeform: the basic scheme was invented around 1980 and hasn't much changed (but for the various heterogeneous 'cheats' thrown in by vendors to help cement lock-in )
asciilifeform: there's ~1 way to do it. and various optional lily gilding.
asciilifeform: most folx making fpga-like things naodays, use 6bit luts
asciilifeform: if make smaller than 4, seems to be (empirically) losing idea, the propagation delays from many small cells eat you alive
asciilifeform: it is possible to have LUTs bigger than 4 ( but naturally cuts down on count )
asciilifeform: anyffin added on this skeleton, is a luxury frill. ( e.g. 'express lanes' that go somewhere other than immediate neighbour, or whatever )
asciilifeform: that's it, this is whole fpga.
asciilifeform: the latter case is for when you want the cell to store a bit.
asciilifeform: the 17th bit controls whether the output goes ~straight~ to the neighbours, or instead through a d-flipflop.
asciilifeform: in cell : 16 bits form 4bit lookup table (i.e. for any concrete 4bit input, there is unique out.) the inputs come from the north/south/east/west neighbours.
asciilifeform: all the shift regs are plugged in, arse to mouth, in 1 chain. to program the chip, you clock in n * 17 bits, where n is how many cell.
asciilifeform: erry type of homogeneous fpga worx on same principle. you have cell, in the cell, a shift register. for simplest example take 17 bits. (will be clear why shortly)
asciilifeform: thinking about it, whole item is simple enuff that it'd fit in a coupla log lines. so i'ma throw in ftr :
asciilifeform: ( i.e. 'taxicab' grid topology, as illustrated in yest. thrd. )
asciilifeform: i suppose i can answer wainot done to date by anyone -- it needs 100% homogeneous structure
asciilifeform: it's entirely trivial from mechanical pov.
asciilifeform: ( why no one ever did this, i have nfi )
asciilifeform: incidentally, while on subj, asciilifeform's napkin model of item has symmetric power/io pins, can go on board in 4 ways. put randomly on ea. board, wainot, then give it correspondingly rotated config cell stream.
asciilifeform: idea being, can be made on chinese conveyor, let'em try an' hide little obama in a 200 transistor cell.
asciilifeform: rrright, hence the fpga model.
asciilifeform: http://btcbase.org/log/2019-04-11#1908219 << hard to picture what 'importance' was left after d00d was cornered into his mousetrap ☝︎
asciilifeform: lol if could 'in kitchen' why would then bother to fpga.
asciilifeform: lol why by hand
asciilifeform: prolly landing in dulles already , pugachev cage ready to roll to scaffold
asciilifeform: ipnojeists already walk around all day in search of 802.11
asciilifeform recalls when the lowest plebe still got 56+kbaud , on land line. then 16kb on '1g', 8 (with lossy compression!) on '2g'. nao next crank of the ratchet.
asciilifeform: electric, gas, etc co, already installed '3g' modems in meters here.