fg-genesis 1 ###########################################################################
fg-genesis 2 ## FUCKGOATS CPLD Makefile. V.3K (December 2016.)
fg-genesis 3 ##
fg-genesis 4 ## This was written for an XC9572XL. It SHOULD work on any gate array of
fg-genesis 5 ## equal or greater size, but no such assurance is given.
fg-genesis 6 ## It SHOULD also work quite well in the form of an ASIC, or in TTL, or
fg-genesis 7 ## using any other reasonably-fast logic element.
fg-genesis 8 ##
fg-genesis 9 ## (C) 2016 No Such lAbs.
fg-genesis 10 ##
fg-genesis 11 ## You do not have, nor can you ever acquire the right to use, copy or
fg-genesis 12 ## distribute this software ; Should you use this software for any purpose,
fg-genesis 13 ## or copy and distribute it to anyone or in any manner, you are breaking
fg-genesis 14 ## the laws of whatever soi-disant jurisdiction, and you promise to
fg-genesis 15 ## continue doing so for the indefinite future. In any case, please
fg-genesis 16 ## always : read and understand any software ; verify any PGP signatures
fg-genesis 17 ## that you use - for any purpose.
fg-genesis 18 ###########################################################################
fg-genesis 19
fg-genesis 20 ###########################################################################
fg-genesis 21 ## make clean && make #<<<<<<<<<<<< build
fg-genesis 22 ## make burn #<<<<<<<<<<<< burn ROM with Xilinx's burner
fg-genesis 23 ###########################################################################
fg-genesis 24
fg-genesis 25 ## Project name
fg-genesis 26 PROJECT=fg
fg-genesis 27 ## Part number
fg-genesis 28 PART=XC9572XL-5-vq44
fg-genesis 29 ## Output configuration file
fg-genesis 30 OUTPUT=$(PROJECT).jed
fg-genesis 31 ## Verilog sources
fg-genesis 32 SOURCES=fg.v
fg-genesis 33 ## Constraints file
fg-genesis 34 UCF=$(PROJECT).ucf
fg-genesis 35
fg-genesis 36 ## Path to Xilinx tools, blank if in $PATH, must end in /
fg-genesis 37 ## YOU MUST CHANGE THIS TO YOURS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
fg-genesis 38 XILINX=/opt/Xilinx/13.1/ISE_DS/ISE/bin/lin64/
fg-genesis 39 ## If you have some OTHER version of the Xilinx turdware, this build MAY work.
fg-genesis 40
fg-genesis 41 WD=work
fg-genesis 42 PB=$(WD)/$(PROJECT)
fg-genesis 43
fg-genesis 44 XSTFLAGS=-opt_mode Speed -opt_level 2 -verilog2001 YES
fg-genesis 45 CPLDFITFLAGS=-slew fast -power std -terminate keeper -unused float -optimize speed -init low
fg-genesis 46
fg-genesis 47 .PHONY: all clean
fg-genesis 48
fg-genesis 49 all: $(PB).tim $(OUTPUT)
fg-genesis 50
fg-genesis 51 $(WD):
fg-genesis 52 mkdir $(WD)/
fg-genesis 53
fg-genesis 54 $(PB).ngc: $(SOURCES)
fg-genesis 55 @[ ! -e $(WD) ] && mkdir $(WD) || true
fg-genesis 56 @echo "Generating $(PB).prj..."
fg-genesis 57 @rm -f $(PB).prj
fg-genesis 58 @for i in $(SOURCES); do \
fg-genesis 59 echo "verilog $(PROJECT) $$i" >> $(PB).prj; \
fg-genesis 60 done
fg-genesis 61 @echo "DEFAULT_SEARCH_ORDER" > $(PB).lso
fg-genesis 62 @echo "set -tmpdir $(WD) -xsthdpdir $(WD)" > $(PB).xst
fg-genesis 63 @echo "run -ifn $(PB).prj -ifmt mixed -top $(PROJECT) -ofn $@ -ofmt NGC -p $(PART) $(XSTFLAGS) -lso $(PB).lso" >> $(PB).xst
fg-genesis 64 $(XILINX)xst -ifn $(PB).xst -ofn $(PB)_xst.log
fg-genesis 65
fg-genesis 66 $(PB).ngd: $(PB).ngc $(UCF)
fg-genesis 67 cd $(WD) ; $(XILINX)ngdbuild -p $(PART) -uc ../$(UCF) ../$< ../$@
fg-genesis 68
fg-genesis 69 $(PB).vm6: $(PB).ngd
fg-genesis 70 cd $(WD) ; $(XILINX)cpldfit -exhaust -p $(PART) ../$<
fg-genesis 71
fg-genesis 72 $(PB).tim: $(PB).vm6
fg-genesis 73 cd $(WD) ; $(XILINX)taengine -l ../$@ -detail -f $(PROJECT) ../$<
fg-genesis 74
fg-genesis 75 $(PB).jed: $(PB).vm6
fg-genesis 76 cd $(WD) ; $(XILINX)hprep6 -i ../$<
fg-genesis 77 @echo "Generating $(PB).cmd..."
fg-genesis 78 @echo "setmode -bscan" > $(PB).cmd
fg-genesis 79 @echo "setcable -p auto" >> $(PB).cmd
fg-genesis 80 @echo "Identify -inferir" >> $(PB).cmd
fg-genesis 81 @echo "ReadIdcode -p 1" >> $(PB).cmd
fg-genesis 82 @echo "assignFile -p 1 -file $(PROJECT).jed" >> $(PB).cmd
fg-genesis 83 @echo "erase -p 1 -o" >> $(PB).cmd
fg-genesis 84 @echo "program -p 1" >> $(PB).cmd
fg-genesis 85 @echo "quit" >> $(PB).cmd
fg-genesis 86
fg-genesis 87 burn:
fg-genesis 88 cd $(WD) ; $(XILINX)impact -batch $(PROJECT).cmd
fg-genesis 89
fg-genesis 90 %: $(WD)/%
fg-genesis 91 @echo "Output $@ is ready"
fg-genesis 92
fg-genesis 93 clean:
fg-genesis 94 rm -rf $(WD) $(OUTPUT) _xmsgs