###########################################################################
## FUCKGOATS CPLD Makefile. V.3K (December 2016.)
##
## This was written for an XC9572XL. It SHOULD work on any gate array of
## equal or greater size, but no such assurance is given.
## It SHOULD also work quite well in the form of an ASIC, or in TTL, or
## using any other reasonably-fast logic element.
##
## (C) 2016 No Such lAbs.
##
## You do not have, nor can you ever acquire the right to use, copy or
## distribute this software ; Should you use this software for any purpose,
## or copy and distribute it to anyone or in any manner, you are breaking
## the laws of whatever soi-disant jurisdiction, and you promise to
## continue doing so for the indefinite future. In any case, please
## always : read and understand any software ; verify any PGP signatures
## that you use - for any purpose.
###########################################################################

###########################################################################
## make clean && make  #<<<<<<<<<<<< build
## make burn           #<<<<<<<<<<<< burn ROM with Xilinx's burner
###########################################################################

## Project name
PROJECT=fg
## Part number
PART=XC9572XL-5-vq44
## Output configuration file
OUTPUT=$(PROJECT).jed
## Verilog sources
SOURCES=fg.v
## Constraints file
UCF=$(PROJECT).ucf

## Path to Xilinx tools, blank if in $PATH, must end in /
## YOU MUST CHANGE THIS TO YOURS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
XILINX=/opt/Xilinx/13.1/ISE_DS/ISE/bin/lin64/
## If you have some OTHER version of the Xilinx turdware, this build MAY work.

WD=work
PB=$(WD)/$(PROJECT)

XSTFLAGS=-opt_mode Speed -opt_level 2 -verilog2001 YES
CPLDFITFLAGS=-slew fast -power std -terminate keeper -unused float -optimize speed -init low

.PHONY: all clean

all: $(PB).tim $(OUTPUT)

$(WD):
	mkdir $(WD)/

$(PB).ngc: $(SOURCES)
	@[ ! -e $(WD) ] && mkdir $(WD) || true
	@echo "Generating $(PB).prj..."
	@rm -f $(PB).prj
	@for i in $(SOURCES); do \
		echo "verilog $(PROJECT) $$i" >> $(PB).prj; \
	done
	@echo "DEFAULT_SEARCH_ORDER" > $(PB).lso
	@echo "set -tmpdir $(WD) -xsthdpdir $(WD)" > $(PB).xst
	@echo "run -ifn $(PB).prj -ifmt mixed -top $(PROJECT) -ofn $@ -ofmt NGC -p $(PART) $(XSTFLAGS) -lso $(PB).lso" >> $(PB).xst
	$(XILINX)xst -ifn $(PB).xst -ofn $(PB)_xst.log

$(PB).ngd: $(PB).ngc $(UCF)
	cd $(WD) ; $(XILINX)ngdbuild -p $(PART) -uc ../$(UCF) ../$< ../$@

$(PB).vm6: $(PB).ngd
	cd $(WD) ; $(XILINX)cpldfit -exhaust -p $(PART) ../$<

$(PB).tim: $(PB).vm6
	cd $(WD) ; $(XILINX)taengine -l ../$@ -detail -f $(PROJECT) ../$<

$(PB).jed: $(PB).vm6
	cd $(WD) ; $(XILINX)hprep6 -i ../$<
	@echo "Generating $(PB).cmd..."
	@echo "setmode -bscan" > $(PB).cmd
	@echo "setcable -p auto" >> $(PB).cmd
	@echo "Identify -inferir" >> $(PB).cmd
	@echo "ReadIdcode -p 1" >> $(PB).cmd
	@echo "assignFile -p 1 -file $(PROJECT).jed" >> $(PB).cmd
	@echo "erase -p 1 -o" >> $(PB).cmd
	@echo "program -p 1" >> $(PB).cmd
	@echo "quit" >> $(PB).cmd

burn:
	cd $(WD) ; $(XILINX)impact -batch $(PROJECT).cmd

%: $(WD)/%
	@echo "Output $@ is ready"

clean:
	rm -rf $(WD) $(OUTPUT) _xmsgs