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+ 2E1120E28077B4FC31BC2DE704CBA9591DAAD2E4193737CF911A0DD49D4731843CC9FB9C3595F65C9E1BDF6A13D2D41011552DE688CFF10A7074ACE6827CC37F
fg.ucf
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5 ///////////////////////////////////////////////////////////////////////////
6 // FUCKGOATS CPLD UCF constraint file. V.3K (December 2016.)
7 //
8 // This was written for an XC9572XL. It SHOULD work on any gate array of
9 // equal or greater size, but no such assurance is given.
10 // It SHOULD also work quite well in the form of an ASIC, or in TTL, or
11 // using any other reasonably-fast logic element.
12 //
13 // (C) 2016 No Such lAbs.
14 //
15 // You do not have, nor can you ever acquire the right to use, copy or
16 // distribute this software ; Should you use this software for any purpose,
17 // or copy and distribute it to anyone or in any manner, you are breaking
18 // the laws of whatever soi-disant jurisdiction, and you promise to
19 // continue doing so for the indefinite future. In any case, please
20 // always : read and understand any software ; verify any PGP signatures
21 // that you use - for any purpose.
22 ///////////////////////////////////////////////////////////////////////////
23
24 // Device : XC9572XL-5-VQ44
25 //
26 // --------------------------------
27 // /44 43 42 41 40 39 38 37 36 35 34 \
28 // | 1 33 |
29 // | 2 32 |
30 // | 3 31 |
31 // | 4 30 |
32 // | 5 XC9572XL-5-VQ44 29 |
33 // | 6 28 |
34 // | 7 27 |
35 // | 8 26 |
36 // | 9 25 |
37 // | 10 24 |
38 // | 11 23 |
39 // \ 12 13 14 15 16 17 18 19 20 21 22 /
40 // --------------------------------
41
42 NET "xtal" LOC = "P1"; // on-board 14.7456MHz resonator
43 NET "clk" LOC = "P33"; // master/slave clk ('RESET' on v1 pcb)
44
45 NET "IN_A" LOC = "P37"; // bottom analogue RNG connector
46 NET "IN_B" LOC = "P18"; // top analogue RNG connector
47
48 NET "ser_tx" LOC = "P28"; // serial out
49 NET "SAD" LOC = "P34"; // red lamp
50
51 ///////////////////////////////////////////////////////////////////////////
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+ 0000B0ABCB2FE3F54B635A846A7E3A8734ED944A54B9CD6BBD9F8696E97734F4FD0D7D82E964F47034F2B3468654027CA488B78EE3914A89F88C59596E0DF133
fg.v
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56 ///////////////////////////////////////////////////////////////////////////
57 // FUCKGOATS CPLD circuit. V.3K (December 2016.)
58 //
59 // This was written for an XC9572XL. It SHOULD work on any gate array of
60 // equal or greater size, but no such assurance is given.
61 // It SHOULD also work quite well in the form of an ASIC, or in TTL, or
62 // using any other reasonably-fast logic element.
63 //
64 // (C) 2016 No Such lAbs.
65 //
66 // You do not have, nor can you ever acquire the right to use, copy or
67 // distribute this software ; Should you use this software for any purpose,
68 // or copy and distribute it to anyone or in any manner, you are breaking
69 // the laws of whatever soi-disant jurisdiction, and you promise to
70 // continue doing so for the indefinite future. In any case, please
71 // always : read and understand any software ; verify any PGP signatures
72 // that you use - for any purpose.
73 ///////////////////////////////////////////////////////////////////////////
74
75 ///////////////////////////////////////////////////////////////////////////
76 // Knobs.
77 ///////////////////////////////////////////////////////////////////////////
78 // BITS of analogue input used to make each BYTE of accum output.
79 // You MAY want to change if you were to use another type of analogue RNG,
80 // particularly one having a different spectrum from the 'TW' board.
81 `define FOLD_RSIZE 4 // size of counter register
82 `define FOLD 4'd15 // bit count
83 ///////////////////////////////////////////////////////////////////////////
84
85
86 // div128, for UART's 115200b on 14.7456MHz crystal.
87 // We also use it as slow clock for the watchdog.
88 module baudgen(clk, clkout);
89 input clk;
90 output clkout;
91
92 reg [6:0] counter = 0;
93 wire clkout;
94
95 always @(posedge clk)
96 begin
97 counter <= counter + 1;
98 end
99 assign clkout = (counter == 7'b1111111);
100 endmodule
101
102
103 // A very simple TX-only UART. 'No user serviceable parts inside.'
104 // No async reset, because nothing good can come of aborting mid-byte.
105 module ser_tx(clk, baud_clk, fire, txbyte, tx, busy);
106 input clk, baud_clk, fire;
107 input [7:0] txbyte;
108 output tx, busy;
109 wire busy;
110
111 // Transmitter state machine
112 reg [3:0] state = 0;
113 wire tx_ready = (state == 0);
114 assign busy = ~tx_ready;
115
116 wire [7:0] txbyteD = txbyte;
117
118 always @(posedge clk)
119 case(state)
120 4'b0000: if(fire) state <= 4'b0001;
121 4'b0001: if(baud_clk) state <= 4'b0100;
122 4'b0100: if(baud_clk) state <= 4'b1000; // start
123 4'b1000: if(baud_clk) state <= 4'b1001; // bit 0
124 4'b1001: if(baud_clk) state <= 4'b1010; // bit 1
125 4'b1010: if(baud_clk) state <= 4'b1011; // bit 2
126 4'b1011: if(baud_clk) state <= 4'b1100; // bit 3
127 4'b1100: if(baud_clk) state <= 4'b1101; // bit 4
128 4'b1101: if(baud_clk) state <= 4'b1110; // bit 5
129 4'b1110: if(baud_clk) state <= 4'b1111; // bit 6
130 4'b1111: if(baud_clk) state <= 4'b0010; // bit 7
131 4'b0010: if(baud_clk) state <= 4'b0000; // stop1
132 4'b0011: if(baud_clk) state <= 4'b0000; // stop2 (off)
133 default: if(baud_clk) state <= 4'b0000;
134 endcase
135
136 reg muxbit;
137 always @(*)
138 case(state[2:0])
139 3'd0: muxbit <= txbyteD[0];
140 3'd1: muxbit <= txbyteD[1];
141 3'd2: muxbit <= txbyteD[2];
142 3'd3: muxbit <= txbyteD[3];
143 3'd4: muxbit <= txbyteD[4];
144 3'd5: muxbit <= txbyteD[5];
145 3'd6: muxbit <= txbyteD[6];
146 3'd7: muxbit <= txbyteD[7];
147 endcase
148
149 reg tx;
150 always @(posedge clk)
151 tx <= (state<4) | (state[3] & muxbit);
152 endmodule
153
154
155 // One way to gather entropy from absolute pulse widths.
156 // This was not feasible in v.10K (it could not rely on synced clk.)
157 module eater(clk, nres, in, valid, out);
158 input clk, nres, in;
159 output valid, out;
160
161 reg [3:0] q;
162 reg out;
163 reg s;
164
165 always @(posedge clk or negedge nres)
166 if (~nres)
167 begin
168 s <= 0;
169 end
170 else
171 begin
172 s <= in;
173 end
174
175 wire pulse = s ^ in; // either rise or fall of input
176
177 always @(posedge clk or negedge nres)
178 if (~nres)
179 begin
180 q <= 0;
181 out <= 0;
182 end
183 else
184 begin
185 out <= q[3] ^ q[2] ^ q[1] ^ q[0];
186 q <= pulse ? 0 : q + 1;
187 end
188
189 assign valid = pulse;
190 endmodule
191 // NOTE that if you are doing a yoke test with two units and one set
192 // of analogue RNGs, you must buffer the latter with a latch clocked
193 // from the common clock, so that they obey the hold time constraint
194 // of the CPLD's input buffer. Without this, operation will ~still~
195 // be repeatable between the yoked units, but ~with errors~.
196
197
198 // Von Neumann's 'fair coin' algorithm.
199 module debias(clk, res, fire, in, valid, out);
200 input clk, res, fire, in;
201 output valid, out;
202
203 reg p, q;
204 reg [1:0] state;
205 wire valid;
206
207 always @(posedge clk or negedge res)
208 if (~res)
209 begin
210 state <= 0;
211 p <= 0;
212 q <= 0;
213 end
214 else
215 begin
216 case(state)
217 2'd0:
218 begin
219 p <= in;
220 state <= fire ? 2'd1 : 2'd0;
221 end
222 2'd1:
223 begin
224 q <= in;
225 state <= fire ? 2'd2 : 2'd1;
226 end
227 2'd2:
228 begin
229 state <= 2'd0;
230 end
231 2'd3: // unused
232 begin
233 state <= 2'd0;
234 end
235 endcase
236 end
237
238 assign valid = (p ^ q) & (state == 2'd2);
239 assign out = p;
240 endmodule
241
242
243 // Byte Accumulator.
244 module accum(clk, nres, fire, in, roll, rdy);
245 parameter fold = 8; // bits per shot
246 parameter count_bits = 4;
247
248 input clk, in, nres, fire;
249 output rdy;
250 output [7:0] roll;
251
252 reg [7:0] roll;
253 reg [count_bits-1:0] bit_count;
254 reg rdy;
255
256 always @(posedge clk or negedge nres)
257 begin
258 if (~nres) // async reset
259 begin
260 bit_count <= 0;
261 roll <= 0;
262 rdy <= 0;
263 end
264 else
265 if (fire)
266 begin
267 roll[bit_count[2:0]] <= roll[bit_count[2:0]] ^ in;
268 bit_count <= bit_count + 1;
269 if (bit_count == fold) rdy <= 1; // raise ready flag
270 end
271 end
272 endmodule
273
274
275 // Watchdog. Counter, stops advancing at max until reset.
276 module dog(clk, nres, run, alarm);
277 input clk, nres, run;
278 output alarm;
279
280 reg [5:0] count;
281
282 assign alarm = (count == 6'b111111);
283
284 always @(posedge clk or negedge nres)
285 begin
286 if (~nres) // async reset
287 begin
288 count <= 0;
289 end
290 else
291 if (run & ~alarm)
292 begin
293 count <= count + 1;
294 end
295 end
296 endmodule
297
298
299 // Werker.
300 module fg(input wire xtal, // on-board clock, from 14.7456MHz resonator
301 inout wire clk, // clock output (master) or input (slave)
302 input wire IN_A, // 'bottom' analogue RNG input, pulled high
303 input wire IN_B, // 'top' analogue RNG input, pulled high
304 output wire ser_tx, // output of UART, to TTL converter
305 output wire SAD // red lamp
306 );
307
308 ///////////////////////////////////////////////////////////////////////////
309 // Serial UART
310 ///////////////////////////////////////////////////////////////////////////
311
312 wire tx;
313 wire fire;
314 wire busy;
315 wire baud_clk;
316 reg [7:0] txbyte;
317
318 // baud clock generator
319 baudgen bg(clk, baud_clk);
320
321 // UART.
322 ser_tx sender(clk, baud_clk, fire, txbyte, tx, busy);
323
324 ///////////////////////////////////////////////////////////////////////////
325 // Master/Slave toggle, for clock-synchronized slave yoke tests.
326 // Yoke two units by connecting the CLK ('RESET' on v1 pcb) pins together.
327 // The first board powered up will become the master.
328 // Slave's red lamp will stay lit, and his clock is inhibited, uses master
329 ///////////////////////////////////////////////////////////////////////////
330 reg [2:0] boot_state = 0;
331
332 // If I master, I output ~my~ clock; otherwise - I slave, wait for a clock:
333 wire am_master = (boot_state == 3'd6);
334 assign clk = am_master ? xtal : 1'bz; // this pin is pulled high
335
336 // Breath of Life
337 always @(posedge xtal) // must use on-board oscillator, for obvious reasons
338 begin
339 case(boot_state)
340 default:
341 begin
342 boot_state <= clk ? boot_state + 1 : 3'd7;
343 end
344 3'd6: // I am a master, for life! (until powerdown)
345 begin
346 boot_state <= 3'd6;
347 end
348 3'd7: // I am a slave, for life! (until powerdown)
349 begin
350 boot_state <= 3'd7;
351 end
352 endcase
353 end
354
355 // we want to hold reset for a short while on bootup
356 reg nreset = 0;
357
358 always @(posedge clk) // use the active clock, ~when we get one~
359 begin
360 if ((~IN_A) & (~IN_B) & baud_clk) // stay in reset until both rng work
361 begin // and until first baud clock pulse
362 nreset <= 1'd1;
363 end
364 end
365
366 // We hold ser_tx low on reset, this way it is easy to see when finished.
367 assign ser_tx = tx & nreset;
368
369 ///////////////////////////////////////////////////////////////////////////
370
371 ///////////////////////////////////////////////////////////////////////////
372 // If this device were to grind to a halt, wouldn't you like to know?
373 ///////////////////////////////////////////////////////////////////////////
374 wire dog_alarm;
375 wire dog_run;
376 wire dog_reset;
377
378 dog sad_dog(clk,
379 dog_reset & nreset, // watchdog reset (if either dips low)
380 dog_run, // watchdog enable-advance
381 dog_alarm); // watchdog alarm, tied to 'SAD' lamp
382 ///////////////////////////////////////////////////////////////////////////
383
384 ///////////////////////////////////////////////////////////////////////////
385 // RNG
386 ///////////////////////////////////////////////////////////////////////////
387 wire eater_a_valid;
388 wire eater_a_out;
389 eater e_a(clk, nreset, IN_A, eater_a_valid, eater_a_out);
390
391 wire eater_b_valid;
392 wire eater_b_out;
393 eater e_b(clk, nreset, IN_B, eater_b_valid, eater_b_out);
394
395 wire valid_a;
396 wire outbit_a;
397
398 debias dbias_a(clk,
399 nreset,
400 eater_a_valid,
401 eater_a_out,
402 valid_a,
403 outbit_a);
404
405 wire valid_b;
406 wire outbit_b;
407
408 debias dbias_b(clk,
409 nreset,
410 eater_b_valid,
411 eater_b_out,
412 valid_b,
413 outbit_b);
414
415 // per xor lemma:
416 wire valid = valid_a | valid_b;
417 wire outbit = outbit_a ^ outbit_b;
418
419 wire acc_res; // reset accum (active low)
420 wire acc_rdy; // accum has byte
421 wire [7:0] acc_byte; // output of accumulator
422
423 accum #(.fold(`FOLD),
424 .count_bits(`FOLD_RSIZE)) acc_a(clk,
425 acc_res & nreset, // if either low
426 valid,
427 outbit,
428 acc_byte,
429 acc_rdy);
430
431 ///////////////////////////////////////////////////////////////////////////
432
433 // device cycles forever through four phases
434 reg [1:0] state;
435
436 always @(posedge clk or negedge nreset)
437 if (~nreset)
438 begin
439 state <= 0;
440 txbyte <= 0;
441 end
442 else
443 begin
444 case(state)
445 2'd0: // ground state
446 begin
447 txbyte <= 0; // clear tx buffer
448 state <= 2'd1; // next
449 end
450 2'd1:
451 begin // wait for 'a' accum
452 if (acc_rdy)
453 begin
454 txbyte <= acc_byte;
455 state <= 2'd2; // next
456 end
457 else
458 state <= 2'd1; // wait
459 end
460 2'd2:
461 begin // clear 'a'; fire tx
462 state <= 2'd3; // next
463 end
464 2'd3:
465 begin // wait to end of tx
466 state <= (~busy) ? 2'd0 : 2'd3; // wait for UART
467 end
468 endcase
469 end
470
471 assign fire = (state == 2'd2); // txbyte is ready, so fire the UART
472 assign acc_res = ~(fire); // zap acc_byte (active low)
473
474 // advance dogometer at the baud clock rate
475 assign dog_run = baud_clk & (state == 2'd1);
476
477 assign dog_reset = acc_res; // reset dogometer we got a byte
478
479 // Red 'Sadness' lamp.
480 // If STEADILY LIT, check ALL connections: the device is halted and is
481 // doing NO USEFUL WORK at all!
482 // Re-seat analogue RNG boards, check their power supplies (if you have,
483 // e.g., a custom isolation system.) Otherwise - one or both analogue
484 // RNG units may need replacement.
485 assign SAD = dog_alarm | ~am_master | (~nreset);
486 // Red lamp will also light if the board is placed into the slave
487 // state (for verification) using the external clock
488 // (marked RESET on early board revs) pin; and when in RESET state.
489 endmodule
490
491 ///////////////////////////////////////////////////////////////////////////
492 ///////////////////////////////////////////////////////////////////////////
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+ F6312358148D7EBEDDDCE03178DB0943D7A753219ECBE0B803407F99A02173E629EF6E8AA9C0F936BA05322461DAE2003E81BEB9A37A3E74F8253C883ACEF43C
Makefile
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497 ###########################################################################
498 ## FUCKGOATS CPLD Makefile. V.3K (December 2016.)
499 ##
500 ## This was written for an XC9572XL. It SHOULD work on any gate array of
501 ## equal or greater size, but no such assurance is given.
502 ## It SHOULD also work quite well in the form of an ASIC, or in TTL, or
503 ## using any other reasonably-fast logic element.
504 ##
505 ## (C) 2016 No Such lAbs.
506 ##
507 ## You do not have, nor can you ever acquire the right to use, copy or
508 ## distribute this software ; Should you use this software for any purpose,
509 ## or copy and distribute it to anyone or in any manner, you are breaking
510 ## the laws of whatever soi-disant jurisdiction, and you promise to
511 ## continue doing so for the indefinite future. In any case, please
512 ## always : read and understand any software ; verify any PGP signatures
513 ## that you use - for any purpose.
514 ###########################################################################
515
516 ###########################################################################
517 ## make clean && make #<<<<<<<<<<<< build
518 ## make burn #<<<<<<<<<<<< burn ROM with Xilinx's burner
519 ###########################################################################
520
521 ## Project name
522 PROJECT=fg
523 ## Part number
524 PART=XC9572XL-5-vq44
525 ## Output configuration file
526 OUTPUT=$(PROJECT).jed
527 ## Verilog sources
528 SOURCES=fg.v
529 ## Constraints file
530 UCF=$(PROJECT).ucf
531
532 ## Path to Xilinx tools, blank if in $PATH, must end in /
533 ## YOU MUST CHANGE THIS TO YOURS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
534 XILINX=/opt/Xilinx/13.1/ISE_DS/ISE/bin/lin64/
535 ## If you have some OTHER version of the Xilinx turdware, this build MAY work.
536
537 WD=work
538 PB=$(WD)/$(PROJECT)
539
540 XSTFLAGS=-opt_mode Speed -opt_level 2 -verilog2001 YES
541 CPLDFITFLAGS=-slew fast -power std -terminate keeper -unused float -optimize speed -init low
542
543 .PHONY: all clean
544
545 all: $(PB).tim $(OUTPUT)
546
547 $(WD):
548 mkdir $(WD)/
549
550 $(PB).ngc: $(SOURCES)
551 @[ ! -e $(WD) ] && mkdir $(WD) || true
552 @echo "Generating $(PB).prj..."
553 @rm -f $(PB).prj
554 @for i in $(SOURCES); do \
555 echo "verilog $(PROJECT) $$i" >> $(PB).prj; \
556 done
557 @echo "DEFAULT_SEARCH_ORDER" > $(PB).lso
558 @echo "set -tmpdir $(WD) -xsthdpdir $(WD)" > $(PB).xst
559 @echo "run -ifn $(PB).prj -ifmt mixed -top $(PROJECT) -ofn $@ -ofmt NGC -p $(PART) $(XSTFLAGS) -lso $(PB).lso" >> $(PB).xst
560 $(XILINX)xst -ifn $(PB).xst -ofn $(PB)_xst.log
561
562 $(PB).ngd: $(PB).ngc $(UCF)
563 cd $(WD) ; $(XILINX)ngdbuild -p $(PART) -uc ../$(UCF) ../$< ../$@
564
565 $(PB).vm6: $(PB).ngd
566 cd $(WD) ; $(XILINX)cpldfit -exhaust -p $(PART) ../$<
567
568 $(PB).tim: $(PB).vm6
569 cd $(WD) ; $(XILINX)taengine -l ../$@ -detail -f $(PROJECT) ../$<
570
571 $(PB).jed: $(PB).vm6
572 cd $(WD) ; $(XILINX)hprep6 -i ../$<
573 @echo "Generating $(PB).cmd..."
574 @echo "setmode -bscan" > $(PB).cmd
575 @echo "setcable -p auto" >> $(PB).cmd
576 @echo "Identify -inferir" >> $(PB).cmd
577 @echo "ReadIdcode -p 1" >> $(PB).cmd
578 @echo "assignFile -p 1 -file $(PROJECT).jed" >> $(PB).cmd
579 @echo "erase -p 1 -o" >> $(PB).cmd
580 @echo "program -p 1" >> $(PB).cmd
581 @echo "quit" >> $(PB).cmd
582
583 burn:
584 cd $(WD) ; $(XILINX)impact -batch $(PROJECT).cmd
585
586 %: $(WD)/%
587 @echo "Output $@ is ready"
588
589 clean:
590 rm -rf $(WD) $(OUTPUT) _xmsgs
-
+ AD61B6FADCBFC33ACCC92D5C9367A032396BFBDE81505E9C9085D4148684BEA7D711983E1A49AF8D3B89784E4FB875471C2A2FA3D148D8DE9A09066595CF65B2
README
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595 The current FUCKGOATS schematics (pcb v1): fg.png
596 sha512:
597 03d8a77e0d5d082f0f40c3bc73fa4f605326d224954b4c75a2bb8c653f260683d8031596f496e6c5aecca7e6380ca1821c3919816c726cefe571680f4eb973ae
598
599
600 The current ANALOGUE RNG schematics (pcb TW): trng_tw.png
601 sha512:
602 f6e19a7afa01f16ed2f40d9154fa10c37a3e188a584cbe892c91216d136958916c89dadabea8ba8fd59a7e536aa04b5f1893096c6f256d146db1c9a23a70aa00
603
604
605 V.3K compiled CPLD turd: fg.jed
606 sha512:
607 af7ae91db33800352408ca66edc08228931bb14864610f8f2bd2c1a587c5e0370f1f5b26f4033be044969d5b225269ba309d3cb5e3f8b584e967002c34de5208
608
609
610 Please read comments in fg.v and http://nosuchlabs.com/hardware.html for operating instructions.