m_genesis.kv 1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
m_genesis.kv 2 ;; ;;
m_genesis.kv 3 ;; This file is part of 'M', a MIPS system emulator. ;;
m_genesis.kv 4 ;; ;;
m_genesis.kv 5 ;; (C) 2019 Stanislav Datskovskiy ( www.loper-os.org ) ;;
m_genesis.kv 6 ;; http://wot.deedbot.org/17215D118B7239507FAFED98B98228A001ABFFC7.html ;;
m_genesis.kv 7 ;; ;;
m_genesis.kv 8 ;; You do not have, nor can you ever acquire the right to use, copy or ;;
m_genesis.kv 9 ;; distribute this software ; Should you use this software for any purpose, ;;
m_genesis.kv 10 ;; or copy and distribute it to anyone or in any manner, you are breaking ;;
m_genesis.kv 11 ;; the laws of whatever soi-disant jurisdiction, and you promise to ;;
m_genesis.kv 12 ;; continue doing so for the indefinite future. In any case, please ;;
m_genesis.kv 13 ;; always : read and understand any software ; verify any PGP signatures ;;
m_genesis.kv 14 ;; that you use - for any purpose. ;;
m_genesis.kv 15 ;; ;;
m_genesis.kv 16 ;; See also http://trilema.com/2015/a-new-software-licensing-paradigm . ;;
m_genesis.kv 17 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
m_genesis.kv 18
m_genesis.kv 19 ;-----------------------------------------------------------------------------
m_genesis.kv 20 ; Value of Program Counter (PC) on Warmup
m_genesis.kv 21 ;-----------------------------------------------------------------------------
m_genesis.kv 22 %define INIT_PC 0xBFC00000 ; Per traditional MIPS standard.
m_genesis.kv 23 ;-----------------------------------------------------------------------------
m_genesis.kv 24
m_genesis.kv 25 ;-----------------------------------------------------------------------------
m_genesis.kv 26 ; # of TLB entries. Could have more; but would have to change not only here.
m_genesis.kv 27 ;-----------------------------------------------------------------------------
m_genesis.kv 28 %define TLB_ENTRIES_COUNT 16 ; in principle could have more.
m_genesis.kv 29 ;-----------------------------------------------------------------------------
m_genesis.kv 30
m_genesis.kv 31 ;-----------------------------------------------------------------------------
m_genesis.kv 32 ; MIPS Exceptions Codes (See CP0_Cause Flags re: where they sit)
m_genesis.kv 33 ;-----------------------------------------------------------------------------
m_genesis.kv 34 %define EXC_Int 0 ; Interrupt
m_genesis.kv 35 %define EXC_Mod 1 ; TLB modification exception
m_genesis.kv 36 %define EXC_TLBL 2 ; TLB exception (load or instruction fetch)
m_genesis.kv 37 %define EXC_TLBS 3 ; TLB exception (store)
m_genesis.kv 38 %define EXC_AdEL 4 ; Address error exception (load or instruction fetch)
m_genesis.kv 39 %define EXC_AdES 5 ; Address error exception (store)
m_genesis.kv 40 %define EXC_IBE 6 ; Bus error exception (instruction fetch)
m_genesis.kv 41 %define EXC_DBE 7 ; Bus error exception (data reference: load or store)
m_genesis.kv 42 %define EXC_SYS 8 ; Syscall exception
m_genesis.kv 43 %define EXC_BP 9 ; Breakpoint exception
m_genesis.kv 44 %define EXC_RI 10 ; Reserved instruction exception
m_genesis.kv 45 %define EXC_CpU 11 ; Coprocessor Unusable exception
m_genesis.kv 46 %define EXC_Ov 12 ; Arithmetic Overflow exception
m_genesis.kv 47 %define EXC_Tr 13 ; Trap exception
m_genesis.kv 48 %define EXC_Watch 23 ; Reference to WatchHi/WatchLo address
m_genesis.kv 49 %define EXC_MCheck 24 ; Machine check
m_genesis.kv 50 ;-----------------------------------------------------------------------------
m_genesis.kv 51
m_genesis.kv 52 ;-----------------------------------------------------------------------------
m_genesis.kv 53 ; MIPS CP0_Cause Register
m_genesis.kv 54 ;-----------------------------------------------------------------------------
m_genesis.kv 55 ; 11111111111111110000000000000000 EEEEE - Exception Code; IIIIIIII - IRQ;
m_genesis.kv 56 ; FEDCBA9876543210FEDCBA9876543210 IV - Indicates whether an interrupt
m_genesis.kv 57 ; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ exception uses the general exception
m_genesis.kv 58 ; B0CC0000IW000000IIIIIIII0EEEEE00 vector or a special interrupt vector:
m_genesis.kv 59 ; D EE VP 76543210 0: General exception vector (0x180)
m_genesis.kv 60 ; 1: Special interrupt vector (0x200)
m_genesis.kv 61 ; BD - Indicates whether last exception taken occurred in a branch delay slot.
m_genesis.kv 62 ; 0: Not in delay slot; 1: In delay slot.
m_genesis.kv 63 ; BD bit is not updated on a new exception if the EXL bit is set.
m_genesis.kv 64 ; IRQ0, IRQ1 -- 'software IRQ'; IRQ2..IRQ7 -- iron IRQ.
m_genesis.kv 65 ; MIPS Timer (powered by CP0_Count and CP0_Compare) is perma-soldered to IRQ7.
m_genesis.kv 66 ;-----------------------------------------------------------------------------
m_genesis.kv 67 %define CP0Cau_IRQ_Bottom 8 ; Index of bit in CP0_Cause where IRQ # lives
m_genesis.kv 68 %define CP0Cau_IV 23 ; Whether exception uses general or special vect
m_genesis.kv 69 %define CP0Cau_BD 31 ; Whether exception occurred in branch delay slt
m_genesis.kv 70 ;-----------------------------------------------------------------------------
m_genesis.kv 71
m_genesis.kv 72 ;-----------------------------------------------------------------------------
m_genesis.kv 73 ; MIPS CP0_Status Register
m_genesis.kv 74 ;-----------------------------------------------------------------------------
m_genesis.kv 75 %define CP0St_CU3 31 ; Coprocessor Access CU3 (unused)
m_genesis.kv 76 %define CP0St_CU2 30 ; Coprocessor Access CU2 (unused)
m_genesis.kv 77 %define CP0St_CU1 29 ; Coprocessor Access CU1 (unused)
m_genesis.kv 78 %define CP0St_CU0 28 ; Coprocessor Access CU0 (unused)
m_genesis.kv 79 %define CP0St_RP 27 ; Reduced Power Mode (unused)
m_genesis.kv 80 %define CP0St_FR 26 ; Floating Point Reg Mode -- Unused on 32-bit MIPS
m_genesis.kv 81 %define CP0St_RE 25 ; Reverse-Endianism (0: user, 1: flipped) - unused
m_genesis.kv 82 %define CP0St_MX 24 ; Unused on 32-bit MIPS
m_genesis.kv 83 %define CP0St_PX 23 ; Unused on 32-bit MIPS
m_genesis.kv 84 %define CP0St_BEV 22 ; BEV (0: Normal Exception Vector, 1: Bootstrap)
m_genesis.kv 85 %define CP0St_TS 21 ; TLB 'multi-match' shutdown (unused)
m_genesis.kv 86 %define CP0St_SR 20 ; Soft Reset (0: not soft, 1: soft)
m_genesis.kv 87 %define CP0St_NMI 19 ; NMI (unused)
m_genesis.kv 88 %define CP0St_IM 8 ; Start of Interrupt Mask (0: IRQ OFF, 1: IRQ ON)
m_genesis.kv 89 %define CP0St_KX 7 ; Unused on 32-bit MIPS
m_genesis.kv 90 %define CP0St_SX 6 ; Unused on 32-bit MIPS
m_genesis.kv 91 %define CP0St_UX 5 ; Unused on 32-bit MIPS
m_genesis.kv 92 %define CP0St_UM 4 ; User Mode (0: Kernel Mode, 1: User Mode)
m_genesis.kv 93 %define CP0St_KSU 3 ; Unused
m_genesis.kv 94 %define CP0St_ERL 2 ; Error Level (0: Normal, 1: Error)
m_genesis.kv 95 %define CP0St_EXL 1 ; Exception Level (0: Normal, 1: Kernel)
m_genesis.kv 96 %define CP0St_IE 0 ; Interrupt Enable
m_genesis.kv 97 ;-----------------------------------------------------------------------------
m_genesis.kv 98
m_genesis.kv 99 ;-----------------------------------------------------------------------------
m_genesis.kv 100 ; MIPS TLB Entry.
m_genesis.kv 101 ; We don't use C0 and C1 anywhere! and so we can put all of it in 32bits:
m_genesis.kv 102 ;-----------------------------------------------------------------------------
m_genesis.kv 103 ; 11111111111111110000000000000000
m_genesis.kv 104 ; FEDCBA9876543210FEDCBA9876543210
m_genesis.kv 105 ; --------------------------------
m_genesis.kv 106 ; GVVDDAAAAAAAAVVVVVVVVVVVVVVVVVVV
m_genesis.kv 107 ; |1010| ASID || VPN2 |
m_genesis.kv 108 ;-----------------------------------------------------------------------------
m_genesis.kv 109 %define TLB_VPN2_Mask 0x7FFFF ; 19 bits
m_genesis.kv 110 %define TLB_ASID_Mask 0xFF ; 8 bits
m_genesis.kv 111 %define TLB_ASID_Shift 19 ; sits after VPN2 Mask
m_genesis.kv 112 %define TLB_D0 27 ; 27th bit
m_genesis.kv 113 %define TLB_D1 28 ; 28th bit
m_genesis.kv 114 %define TLB_V0 29 ; 29th bit
m_genesis.kv 115 %define TLB_V1 30 ; 30th bit
m_genesis.kv 116 %define TLB_G 31 ; 31st bit (last)
m_genesis.kv 117 ;-----------------------------------------------------------------------------