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m_genesis.kv            1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
m_genesis.kv 2 ;; ;;
m_genesis.kv 3 ;; This file is part of 'M', a MIPS system emulator. ;;
m_genesis.kv 4 ;; ;;
m_genesis.kv 5 ;; (C) 2019 Stanislav Datskovskiy ( www.loper-os.org ) ;;
m_genesis.kv 6 ;; http://wot.deedbot.org/17215D118B7239507FAFED98B98228A001ABFFC7.html ;;
m_genesis.kv 7 ;; ;;
m_genesis.kv 8 ;; You do not have, nor can you ever acquire the right to use, copy or ;;
m_genesis.kv 9 ;; distribute this software ; Should you use this software for any purpose, ;;
m_genesis.kv 10 ;; or copy and distribute it to anyone or in any manner, you are breaking ;;
m_genesis.kv 11 ;; the laws of whatever soi-disant jurisdiction, and you promise to ;;
m_genesis.kv 12 ;; continue doing so for the indefinite future. In any case, please ;;
m_genesis.kv 13 ;; always : read and understand any software ; verify any PGP signatures ;;
m_genesis.kv 14 ;; that you use - for any purpose. ;;
m_genesis.kv 15 ;; ;;
m_genesis.kv 16 ;; See also http://trilema.com/2015/a-new-software-licensing-paradigm . ;;
m_genesis.kv 17 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
m_genesis.kv 18
m_genesis.kv 19 ;-----------------------------------------------------------------------------
m_genesis.kv 20 ;; State
m_genesis.kv 21 ;-----------------------------------------------------------------------------
m_genesis.kv 22 section .bss
m_genesis.kv 23 SlaveIRQ resd 1 ; External Interrupt from Slaves
m_genesis.kv 24 ;-----------------------------------------------------------------------------
m_genesis.kv 25
m_genesis.kv 26 section .text
m_genesis.kv 27
m_genesis.kv 28 ;-----------------------------------------------------------------------------
m_genesis.kv 29 ; SetIRQ : Trigger External Interrupt ( Parameter: constant IRQ # )
m_genesis.kv 30 ;-----------------------------------------------------------------------------
m_genesis.kv 31 %macro SetIRQ 1 ; param is the IRQ #
m_genesis.kv 32 bts CP0_Cause, (CP0Cau_IRQ_Bottom + %1)
m_genesis.kv 33 %endmacro
m_genesis.kv 34 ;-----------------------------------------------------------------------------
m_genesis.kv 35
m_genesis.kv 36 ;-----------------------------------------------------------------------------
m_genesis.kv 37 ; ClrIRQ : Clear External Interrupt ( Parameter: constant IRQ # )
m_genesis.kv 38 ;-----------------------------------------------------------------------------
m_genesis.kv 39 %macro ClrIRQ 1 ; param is the IRQ #
m_genesis.kv 40 btr CP0_Cause, (CP0Cau_IRQ_Bottom + %1)
m_genesis.kv 41 %endmacro
m_genesis.kv 42 ;-----------------------------------------------------------------------------
m_genesis.kv 43
m_genesis.kv 44 ;-----------------------------------------------------------------------------
m_genesis.kv 45 ; Built-In Iron IRQs:
m_genesis.kv 46 ;-----------------------------------------------------------------------------
m_genesis.kv 47 %define TIMER_IRQ 7 ; MIPS Timer (trigger when CP0_Count==CP0_Compare)
m_genesis.kv 48 ;-----------------------------------------------------------------------------
m_genesis.kv 49
m_genesis.kv 50 ;-----------------------------------------------------------------------------
m_genesis.kv 51 ; IRQ from Slave:
m_genesis.kv 52 ;; TODO: locking and wait/sleep
m_genesis.kv 53 ;-----------------------------------------------------------------------------
m_genesis.kv 54 %macro SetSlaveIRQ 1
m_genesis.kv 55 bts dword [SlaveIRQ], (CP0Cau_IRQ_Bottom + %1)
m_genesis.kv 56 %endmacro
m_genesis.kv 57 ;-----------------------------------------------------------------------------
m_genesis.kv 58
m_genesis.kv 59 ;-----------------------------------------------------------------------------
m_genesis.kv 60 ; Poll for any Slave IRQ:
m_genesis.kv 61 ;-----------------------------------------------------------------------------
m_genesis.kv 62 %macro GetSlaveIRQ 0
m_genesis.kv 63 mov eax, [SlaveIRQ] ; Get the Slave IRQ shadow register
m_genesis.kv 64 test eax, eax ; Is it zero?
m_genesis.kv 65 jz %%skip ; If was zero, skip;
m_genesis.kv 66 mov dword [SlaveIRQ], 0 ; Else, 1) Zero shadow register
m_genesis.kv 67 or CP0_Cause, eax ; 2) OR it into CP0_Cause.
m_genesis.kv 68 %%skip:
m_genesis.kv 69 %endmacro
m_genesis.kv 70 ;-----------------------------------------------------------------------------