/////////////////////////////////////////////////////////////////////////// // FUCKGOATS CPLD UCF constraint file. V.3K (December 2016.) // // This was written for an XC9572XL. It SHOULD work on any gate array of // equal or greater size, but no such assurance is given. // It SHOULD also work quite well in the form of an ASIC, or in TTL, or // using any other reasonably-fast logic element. // // (C) 2016 No Such lAbs. // // You do not have, nor can you ever acquire the right to use, copy or // distribute this software ; Should you use this software for any purpose, // or copy and distribute it to anyone or in any manner, you are breaking // the laws of whatever soi-disant jurisdiction, and you promise to // continue doing so for the indefinite future. In any case, please // always : read and understand any software ; verify any PGP signatures // that you use - for any purpose. /////////////////////////////////////////////////////////////////////////// // Device : XC9572XL-5-VQ44 // // -------------------------------- // /44 43 42 41 40 39 38 37 36 35 34 \ // | 1 33 | // | 2 32 | // | 3 31 | // | 4 30 | // | 5 XC9572XL-5-VQ44 29 | // | 6 28 | // | 7 27 | // | 8 26 | // | 9 25 | // | 10 24 | // | 11 23 | // \ 12 13 14 15 16 17 18 19 20 21 22 / // -------------------------------- NET "xtal" LOC = "P1"; // on-board 14.7456MHz resonator NET "clk" LOC = "P33"; // master/slave clk ('RESET' on v1 pcb) NET "IN_A" LOC = "P37"; // bottom analogue RNG connector NET "IN_B" LOC = "P18"; // top analogue RNG connector NET "ser_tx" LOC = "P28"; // serial out NET "SAD" LOC = "P34"; // red lamp ///////////////////////////////////////////////////////////////////////////