asciilifeform: mats: i can trivially make mincemeat of this by issuing raw dma cycles. ☟︎

asciilifeform: and ideally you'd want one that doesn't dma

asciilifeform: 'the Management Engine... is a separate microcontroller embedded in the PCH and has a full network stack, has access to DMA and other nasty things. The firmware is signed by Intel and verified at each boot by the microcontroller, and if the firmware signature fails to verify correctly, the x86 cpu will not be allowed to boot... We must get that freed by Intel' << lol!!!

asciilifeform: ('pio' - programmed i/o, mode of using standard 'ata' without dma. used by simple schoolboy operating systems for x86)

asciilifeform: last version i read, disk i/o was implemented via 'pio' vs dma, so not optimal. but ought to suffice for just about any practical use.

asciilifeform: with possibly a little dma magic on transmitting and receiving ends.

asciilifeform: wetware DMA ?

asciilifeform: that is, not the fact of dma being satanic in and of itself (it isn't), but just how thoroughly hardware designers are enslaved by architectural oddness beyond their control.

asciilifeform: since a 'von-neumann style' cpu cannot guarantee 'paying attention' for a sufficiently-large N of cycles, we get dma.

asciilifeform: DMA is also not really confined to PC arch; there's the fact that all recent (20 yrs. or so) DRAM works best in 'burst mode'

asciilifeform: re: DMA: it, in itself, is not the problem. the problem, as always, is in the 'mouse-breeding kitchen' of the PC arch. in general.

asciilifeform: mircea_popescu: re: 'strategic...' piece: DMA is an artifact from single-cpu days.

asciilifeform: tldr ver.: drive bus DMA over NIC with diddled ROM.